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From: Heiko Stuebner <heiko@sntech.de>
To: Kever Yang <kever.yang@rock-chips.com>,
	Elaine Zhang <zhangqing@rock-chips.com>,
	Peter Geis <pgwipeout@gmail.com>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH] clk: rockchip: fix rk3568 cpll clk gate bits
Date: Mon, 24 May 2021 01:51:10 +0200	[thread overview]
Message-ID: <162181382840.2545380.4133939469375306641.b4-ty@sntech.de> (raw)
In-Reply-To: <20210519174149.3691335-1-pgwipeout@gmail.com>

On Wed, 19 May 2021 13:41:49 -0400, Peter Geis wrote:
> The cpll clk gate bits had an ordering issue. This led to the loss of
> the boot sdmmc controller when the gmac was shut down with:
> `ip link set eth0 down`
> as the cpll_100m was shut off instead of the cpll_62p5.
> cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
> misplaced.
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: fix rk3568 cpll clk gate bits
      commit: 2f3877d609e7951ef96d24979eb9d163f1f004f8

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

      parent reply	other threads:[~2021-05-23 23:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19 17:41 Peter Geis
2021-05-20  1:26 ` elaine.zhang
2021-05-23 23:51 ` Heiko Stuebner [this message]

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