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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id a18sm24360812wrh.25.2019.10.01.06.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 06:33:05 -0700 (PDT) References: <20190921151835.770263-1-martin.blumenstingl@googlemail.com> <1jsgons4wy.fsf@starbuckisacylon.baylibre.com> User-agent: mu4e 1.3.3; emacs 26.2 From: Jerome Brunet To: Martin Blumenstingl Cc: Neil Armstrong , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b In-reply-to: Date: Tue, 01 Oct 2019 15:33:04 +0200 Message-ID: <1jeezwr3ov.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Mon 23 Sep 2019 at 22:49, Martin Blumenstingl wrote: > Hi Jerome, > > On Mon, Sep 23, 2019 at 12:06 PM Jerome Brunet wrote: >> >> On Sat 21 Sep 2019 at 17:18, Martin Blumenstingl wrote: >> >> > Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS >> > registers. This series: >> > - adds support for this DDR clock controller (patches 0 and 1) >> > - wires up the DDR PLL as input for two audio clocks (patches 2 and 3) >> >> Have you been able to validate somehow that DDR rate calculated by CCF >> is the actual rate that gets to the audio clocks ? > no, I haven't been able to validate this (yet) > >> While I understand the interest for completeness, I suspect the having >> the DDR clock as an audio parent was just for debugging purpose. IOW, >> I'm not sure if adding this parent is useful to an actual audio use >> case. As far as audio would be concerned, I think we are better of >> without this parent. > there at least three other (potential) consumers of the ddr_pll clocks > on the 32-bit SoCs: > - CPU clock mux [0] > - clk81 mux [1] > - USB PHY [2] > > I have not validated any of these either > Then I would suggest to leave patch 4 out until we can somehow validate this. > > > Martin > > > [0] https://github.com/endlessm/u-boot-meson/blob/345ee7eb02903f5ecb1173ffb2cd36666e44ebed/board/amlogic/m8b_m201_v1/firmware/timming.c#L441 > [1] https://github.com/endlessm/u-boot-meson/blob/345ee7eb02903f5ecb1173ffb2cd36666e44ebed/board/amlogic/m8b_m201_v1/firmware/timming.c#L452 > [2] https://github.com/endlessm/u-boot-meson/blob/f1ee03e3f7547d03e1478cc1fc967a9e5a121d92/arch/arm/cpu/aml_meson/m8/firmware/usb_boot/platform.c#L22