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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id s16sm2586587wrn.78.2020.01.10.07.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2020 07:36:59 -0800 (PST) References: <20191227094606.143637-1-jian.hu@amlogic.com> <20191227094606.143637-2-jian.hu@amlogic.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Jian Hu , Neil Armstrong Cc: Kevin Hilman , "Rob Herring" , Martin Blumenstingl , Michael Turquette , Stephen Boyd , Qiufang Dai , Jianxin Pan , Victor Wan , Chandle Zou , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 1/5] dt-bindings: clock: meson: add A1 PLL clock controller bindings In-reply-to: <20191227094606.143637-2-jian.hu@amlogic.com> Date: Fri, 10 Jan 2020 16:36:58 +0100 Message-ID: <1jftgnz5k5.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Fri 27 Dec 2019 at 10:46, Jian Hu wrote: Please read Documentation/devicetree/writing-schema.rst, run the test and make the necessary correction. > Add the documentation to support Amlogic A1 PLL clock driver, > and add A1 PLL clock controller bindings. > > Signed-off-by: Jian Hu > --- > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 54 +++++++++++++++++++ > include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++ > 2 files changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > new file mode 100644 > index 000000000000..7a327bb174b8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings > + > +maintainers: > + - Neil Armstrong > + - Jerome Brunet > + - Jian Hu > + > +properties: > + compatible: > + const: amlogic,a1-pll-clkc > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > +clocks: > + maxItems: 2 > + items: > + - description: Input xtal_fixpll > + - description: Input xtal_hifipll > + > +clock-names: > + maxItems: 2 > + items: > + - const: xtal_fixpll > + - const: xtal_hifipll > + > +required: > + - compatible > + - "#clock-cells" > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + clkc_pll: pll-clock-controller@7c80 { > + compatible = "amlogic,a1-pll-clkc"; > + reg = <0 0x7c80 0 0x18c>; > + #clock-cells = <1>; > + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>, > + <&clkc_periphs CLKID_XTAL_HIFIPLL>; > + clock-names = "xtal_fixpll", "xtal_hifipll"; > + }; > diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h > new file mode 100644 > index 000000000000..58eae237e503 > --- /dev/null > +++ b/include/dt-bindings/clock/a1-pll-clkc.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ > +/* > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. > + */ > + > +#ifndef __A1_PLL_CLKC_H > +#define __A1_PLL_CLKC_H > + > +#define CLKID_FIXED_PLL 1 > +#define CLKID_FCLK_DIV2 6 > +#define CLKID_FCLK_DIV3 7 > +#define CLKID_FCLK_DIV5 8 > +#define CLKID_FCLK_DIV7 9 > +#define CLKID_HIFI_PLL 10 > + > +#endif /* __A1_PLL_CLKC_H */