From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: narmstrong@baylibre.com, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
Date: Tue, 01 Oct 2019 15:15:10 +0200 [thread overview]
Message-ID: <1jimp8r4ip.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20190921150411.767290-1-martin.blumenstingl@googlemail.com>
On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will let the common clock framework select the
> best matching parent clock if we want that.
>
> This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
> drivers, which both also specify CLK_SET_RATE_PARENT.
>
> Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Applied, Thx
prev parent reply other threads:[~2019-10-01 13:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-21 15:04 [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate Martin Blumenstingl
2019-09-23 8:38 ` Jerome Brunet
2019-10-01 13:15 ` Jerome Brunet [this message]
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