From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
To: <gregkh@linuxfoundation.org>
Cc: <stefan@agner.ch>, <shawnguo@kernel.org>, <kernel@pengutronix.de>,
<mturquette@baylibre.com>, <sboyd@codeaurora.org>,
<jslaby@suse.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-serial@vger.kernel.org>,
Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Subject: [PATCH v2 5/9] tty: serial: fsl_lpuart: Fix broken 8m/s1 support
Date: Tue, 28 Jun 2016 11:02:31 +0530 [thread overview]
Message-ID: <20160628053235.5114-6-bhuvanchandra.dv@toradex.com> (raw)
In-Reply-To: <20160628053235.5114-1-bhuvanchandra.dv@toradex.com>
By default the driver always configure the mode as 8s1 even when 8m1 mode is
selected. Fix this by adding support to control the space/mark bit.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
---
drivers/tty/serial/fsl_lpuart.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 97c1fda..615f191 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -1220,13 +1220,14 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
{
struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
unsigned long flags;
- unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+ unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
unsigned int baud;
unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
unsigned int sbr, brfa;
cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
old_cr2 = readb(sport->port.membase + UARTCR2);
+ cr3 = readb(sport->port.membase + UARTCR3);
cr4 = readb(sport->port.membase + UARTCR4);
bdh = readb(sport->port.membase + UARTBDH);
modem = readb(sport->port.membase + UARTMODEM);
@@ -1274,7 +1275,10 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
if ((termios->c_cflag & PARENB)) {
if (termios->c_cflag & CMSPAR) {
cr1 &= ~UARTCR1_PE;
- cr1 |= UARTCR1_M;
+ if (termios->c_cflag & PARODD)
+ cr3 |= UARTCR3_T8;
+ else
+ cr3 &= ~UARTCR3_T8;
} else {
cr1 |= UARTCR1_PE;
if ((termios->c_cflag & CSIZE) == CS8)
@@ -1342,6 +1346,7 @@ lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
writeb(cr4 | brfa, sport->port.membase + UARTCR4);
writeb(bdh, sport->port.membase + UARTBDH);
writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+ writeb(cr3, sport->port.membase + UARTCR3);
writeb(cr1, sport->port.membase + UARTCR1);
writeb(modem, sport->port.membase + UARTMODEM);
--
2.9.0
next prev parent reply other threads:[~2016-06-28 5:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-28 5:32 [PATCH v2 0/9] Improve Rx/Tx DMA implementation Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 1/9] tty: serial: fsl_lpuart: consider TX FIFO too in tx_empty Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 2/9] clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode Bhuvanchandra DV
2016-07-08 18:40 ` Michael Turquette
2016-06-28 5:32 ` [PATCH v2 3/9] tty: serial: fsl_lpuart: support suspend/resume Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 4/9] tty: serial: fsl_lpuart: fix clearing of receive flag Bhuvanchandra DV
2016-06-28 5:32 ` Bhuvanchandra DV [this message]
2016-06-28 5:32 ` [PATCH v2 6/9] tty: serial: fsl-lpuart: Use cyclic DMA for Rx Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 7/9] tty: serial: fsl-lpuart: Use scatter/gather DMA for Tx Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 8/9] tty: serial: fsl-lpuart: Update suspend/resume for DMA mode Bhuvanchandra DV
2016-06-28 5:32 ` [PATCH v2 9/9] tty: serial: fsl_lpuart: Add support for RS-485 Bhuvanchandra DV
2016-07-04 6:24 ` [PATCH v2 0/9] Improve Rx/Tx DMA implementation Bhuvanchandra DV
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