From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-sunxi@googlegroups.com
Subject: Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
Date: Thu, 28 Sep 2017 12:27:52 +0200 [thread overview]
Message-ID: <20170928102752.ceo54qccqakb4xyx@flea> (raw)
In-Reply-To: <20170923001531.14285-2-icenowy@aosc.io>
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Hi,
On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:
> The A64 PLL_CPU clock has the same instability if some factor changed
> without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
> H3.
>
> Add the mux and pll notifiers for A64 CPU clock to workaround the
> problem.
>
> Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 +++++++++++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index 2bb4cabf802f..b55fa69dd0c1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
> .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
> };
>
> +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
> + .common = &pll_cpux_clk.common,
> + /* copy from pll_cpux_clk */
> + .enable = BIT(31),
> + .lock = BIT(28),
> +};
> +
> +static struct ccu_mux_nb sun50i_a64_cpu_nb = {
> + .common = &cpux_clk.common,
> + .cm = &cpux_clk.mux,
> + .delay_us = 1, /* > 8 clock cycles at 24 MHz */
> + .bypass_index = 1, /* index of 24 MHz oscillator */
> +};
> +
>
> static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> {
> struct resource *res;
> void __iomem *reg;
> u32 val;
> + int ret;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> reg = devm_ioremap_resource(&pdev->dev, res);
> @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
>
> writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
>
> - return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
> + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
> + if (ret)
> + return ret;
> +
> + /* Gate then ungate PLL CPU after any rate changes */
> + ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
> +
> + /* Reparent CPU during PLL CPU rate changes */
> + ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
> + &sun50i_a64_cpu_nb);
> +
> + return 0;
So this is the fourth user of the exact same code, can you turn that
into a shared function?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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next prev parent reply other threads:[~2017-09-28 10:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-23 0:15 [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC Icenowy Zheng
2017-09-23 0:15 ` [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock Icenowy Zheng
2017-09-28 10:27 ` Maxime Ripard [this message]
2017-09-28 10:42 ` icenowy
2017-09-28 14:20 ` Maxime Ripard
2017-09-28 14:24 ` icenowy
2017-09-28 14:31 ` Maxime Ripard
2017-09-23 0:15 ` [PATCH 2/3] arm64: allwinner: a64: add CPU opp table Icenowy Zheng
2017-09-25 17:38 ` [linux-sunxi] " Samuel Holland
2017-09-23 0:15 ` [PATCH 3/3] arm64: allwinner: a64: set CPU regulator for Pine64 Icenowy Zheng
2017-09-25 10:10 ` [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC Maxime Ripard
2017-09-25 10:12 ` Icenowy Zheng
2017-09-25 10:27 ` Maxime Ripard
2017-09-25 10:29 ` [linux-sunxi] " Icenowy Zheng
2017-09-25 10:43 ` Maxime Ripard
2017-09-27 11:51 ` icenowy
2017-09-28 10:28 ` Maxime Ripard
2020-01-04 6:35 [PATCH 0/3] arm64: allwinner: a64: Enable DVFS on A64 Vasily Khoruzhick
2020-01-04 6:35 ` [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock Vasily Khoruzhick
2020-01-04 6:42 ` Vasily Khoruzhick
2020-01-04 8:18 ` Maxime Ripard
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