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spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728255AbeI1AFY (ORCPT ); Thu, 27 Sep 2018 20:05:24 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:45233 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727307AbeI1AFY (ORCPT ); Thu, 27 Sep 2018 20:05:24 -0400 Received: by mail-io1-f67.google.com with SMTP id e12-v6so2482817iok.12 for ; Thu, 27 Sep 2018 10:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OBWRnqY8VjCI4bodmPyr9voKbRjCxPSITWLW6TzZFjE=; b=IhfmQYfmvdRDId02yUyGnqIaAnCt1sBulgYElSaKRhRYQgDg+Ye91OHGoZEQQ2XFYi boHK8awyjMNr2qhHUg+zeit4mJ8Lx1fgqhbqzpc0zihbE9gOzKXGrEXCxLQ3bp45Yjpx QB+H57C+D5kgQHH++lgHToii/CLOn5UakInmM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OBWRnqY8VjCI4bodmPyr9voKbRjCxPSITWLW6TzZFjE=; b=k89qbkhDsaSdVADNMWjvZNjruVO61nJr0+EOm/z8UYX2GSYZU4MjpBFot++dsYi3qf /o05UWtFRhbSNoM4deWMEfo/S06g2aXj9mCalNHQG08dDtiq5xisc1enZhWVCmU6283b FV0d+1OD6vSw0Hrz6jrx5e2WoPlluhbg47NH7TVlzbBk7aMRvYEBppX8K3uZam2kVMvq 1r0wz2zgVduhT3grRW4O4u5w+cr9nNrDFb7QVz4DtH37oI10ZoYaY1DzvP2u7IEzMs1O qlPB8LQ0MThU90bGbjSI+QlZIwLV0hPWnPvasvn7H/r6WCcB1IwJfx0JSHTAMLc+zTwl zcgQ== X-Gm-Message-State: ABuFfogLAYUF+ix7eXzES5VuNSiG7y3hP7jwXQAQbPy3pyJF6ayuMyl7 3oy1pBj4DjA8jhf7oKf65kbOWCmXMHR5ueyAgBrQmw== X-Google-Smtp-Source: ACcGV60m6SJPSNB8YVbB9s0eAwtjTqAWq3wdH0AnV95wqttR+LrVl9EB7mpo5DcHh+rayCs2m57CLKSUWfuUf2K5C8g= X-Received: by 2002:a6b:b383:: with SMTP id c125-v6mr9775129iof.267.1538070361145; Thu, 27 Sep 2018 10:46:01 -0700 (PDT) MIME-Version: 1.0 References: <20180927114850.24565-1-jagan@amarulasolutions.com> <20180927114850.24565-8-jagan@amarulasolutions.com> <20180927165853.dpluekbqzat663q7@flea> In-Reply-To: <20180927165853.dpluekbqzat663q7@flea> From: Jagan Teki Date: Thu, 27 Sep 2018 23:15:50 +0530 Message-ID: Subject: Re: [PATCH 07/12] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits To: Maxime Ripard Cc: Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Vasily Khoruzhick , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel , Michael Turquette , Stephen Boyd , linux-clk , Michael Trimarchi , linux-arm-kernel , devicetree , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Message-ID: <20180927174550.rUuep0dDGM0PscpG21iPT2tOrkk2A_2raSupbOmeKKE@z> On Thu, Sep 27, 2018 at 10:28 PM Maxime Ripard wrote: > > On Thu, Sep 27, 2018 at 05:18:45PM +0530, Jagan Teki wrote: > > TCON DRQ set bits for non-burst DSI mode can computed via > > horizontal front porch instead of front porch + sync timings. > > > > Since there no documentation for TCON_DRQ_REG(0x7c) register > > this change is taken as reference from BPI-M64-bsp. > > Detailing more what the issue is would be great. > > > Signed-off-by: Jagan Teki > > --- > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > index 599284971ab6..9918fdb990ff 100644 > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > > @@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, > > struct mipi_dsi_device *device = dsi->device; > > u32 val = 0; > > The computation here is in the A64 driver: > > if ((panel->lcd_ht - panel->lcd_x - panel->lcd_hbp) < 21) { > dsi_dev[sel]->dsi_tcon_drq.bits.drq_mode = 0; > } else { > dsi_dev[sel]->dsi_tcon_drq.bits.drq_set = > (panel->lcd_ht-panel->lcd_x-panel->lcd_hbp-20) * > dsi_pixel_bits[panel->lcd_dsi_format]/(8*4); > } > > It is testing that the sync + front porch is smaller than 21, and > otherwise sets the drq. > > > - if ((mode->hsync_end - mode->hdisplay) > 20) { > > My code here is testing that the difference between hsync_end and > hdisplay is superior to 20, and sets the DRQ if true. The condition is > reversed, but otherwise, that difference is the front porch plus the > sync length. True, I understand this, but does drq setting here is specific to SoC? I thought of finding DRQ in A31 BSP but I couldn't find the code. do you have bsp somewhere in github? > > > + if ((mode->hsync_start - mode->hdisplay) > 20) { > > However, you are testing for just the front porch, unlike what your > commit log is saying, and unlike what allwinner's code is saying. So > this deserves some explanation. but A64 is doing this, do you think it's completely A64 specific or testing panel with front porch drq?