From: Thierry Reding <thierry.reding@gmail.com>
To: Joseph Lo <josephl@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 00/19] Tegra210 DFLL support
Date: Tue, 4 Dec 2018 16:10:59 +0100 [thread overview]
Message-ID: <20181204151059.GA23827@ulmo> (raw)
In-Reply-To: <20181204092548.3038-1-josephl@nvidia.com>
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On Tue, Dec 04, 2018 at 05:25:29PM +0800, Joseph Lo wrote:
> This series introduces support for the DFLL as a CPU clock source
> on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which
> is driven directly by the DFLLs PWM output, we also introduce support
> for PWM regulators next to I2C controlled regulators. The DFLL output
> frequency is directly controlled by the regulator voltage. The registers
> for controlling the PWM are part of the DFLL IP block, so there's no
> separate linux regulator object involved because the regulator IC only
> supplies the rail powering the CPUs. It doesn't have any other controls.
>
> The patch 1~4 are the patches of DT bindings update for DFLL clock and
> Tegra124 cpufreq, which add PWM and Tegra210 support for DFLL clock and
> remove deprecate properties for Tegra124 cpufreq bindings.
>
> The patch 5~10 are the patches for DFLL clock driver update for PWM-mode
> DFLL support.
>
> The patch 11 and 12 are the Tegra124 cpufreq driver update to make it
> work with Tegra210.
>
> The patch 13~18 are the devicetree files update for Tegra210 SoC and
> platforms. Two platforms are updated here for different DFLL mode usage.
> The Tegra210-p2371-2180 (a.k.a. Jetson Tx1) uses DFLL-PWM and the
> Tegra210-smaug (a.k.a. Pixel C) uses DFLL-I2C. So two different modes
> are verified with this series.
>
> The patch 19 is the patch for enabling the CPU regulator for Smaug
> board.
>
> Joseph Lo (16):
> dt-bindings: clock: tegra124-dfll: add Tegra210 support
> dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required
> properties
> dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required
> properties
> clk: tegra: dfll: CVB calculation alignment with the regulator
> clk: tegra: dfll: support PWM regulator control
> clk: tegra: dfll: round down voltages based on alignment
> clk: tegra: dfll: add CVB tables for Tegra210
> cpufreq: tegra124: do not handle the CPU rail
> cpufreq: tegra124: extend to support Tegra210
> arm64: dts: tegra210: add DFLL clock
> arm64: dts: tegra210: add CPU clocks
> arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support
> arm64: dts: tegra210-p2371-2180: enable DFLL clock
> arm64: dts: tegra210-smaug: add CPU power rail regulator
> arm64: dts: tegra210-smaug: enable DFLL clock
> arm64: defconfig: Enable MAX8973 regulator
>
> Peter De Schrijver (3):
> dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM
> regulator
> clk: tegra: dfll: registration for multiple SoCs
> clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
>
> .../bindings/clock/nvidia,tegra124-dfll.txt | 77 ++-
> .../cpufreq/nvidia,tegra124-cpufreq.txt | 6 +-
> .../boot/dts/nvidia/tegra210-p2371-2180.dts | 20 +
> .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 +
> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 31 +
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 25 +
> arch/arm64/configs/defconfig | 1 +
> drivers/clk/tegra/Kconfig | 5 +
> drivers/clk/tegra/Makefile | 2 +-
> drivers/clk/tegra/clk-dfll.c | 455 ++++++++++++---
> drivers/clk/tegra/clk-dfll.h | 6 +-
> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 536 +++++++++++++++++-
> drivers/clk/tegra/cvb.c | 12 +-
> drivers/clk/tegra/cvb.h | 7 +-
> drivers/cpufreq/Kconfig.arm | 2 +-
> drivers/cpufreq/tegra124-cpufreq.c | 29 +-
> 16 files changed, 1095 insertions(+), 133 deletions(-)
Hi Joseph,
can you highlight the build and runtime dependencies between the various
patches? For example, can I pick up all the arch/arm64 patches into the
Tegra tree without breaking anything?
Thierry
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next prev parent reply other threads:[~2018-12-04 15:11 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 9:25 [PATCH 00/19] Tegra210 DFLL support Joseph Lo
2018-12-04 9:25 ` [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-07 13:41 ` Jon Hunter
2018-12-10 8:49 ` Joseph Lo
2018-12-10 8:59 ` Jon Hunter
2018-12-10 9:31 ` Joseph Lo
2018-12-10 9:44 ` Jon Hunter
2018-12-11 1:28 ` Joseph Lo
2018-12-11 9:16 ` Peter De Schrijver
2018-12-11 9:36 ` Joseph Lo
2018-12-11 9:15 ` Peter De Schrijver
2018-12-11 11:52 ` Jon Hunter
2018-12-12 1:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 02/19] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-07 13:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 03/19] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-04 15:36 ` Peter De Schrijver
2018-12-05 3:05 ` Joseph Lo
2018-12-05 9:37 ` Peter De Schrijver
2018-12-07 13:52 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 04/19] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-04 15:37 ` Peter De Schrijver
2018-12-05 3:10 ` Joseph Lo
2018-12-07 13:53 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 05/19] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-07 13:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 06/19] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-07 14:10 ` Jon Hunter
2018-12-11 6:23 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 07/19] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-04 15:53 ` Peter De Schrijver
2018-12-05 6:14 ` Joseph Lo
2018-12-07 14:26 ` Jon Hunter
2018-12-11 6:36 ` Joseph Lo
2018-12-07 15:09 ` Jon Hunter
2018-12-11 6:37 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 08/19] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-04 15:46 ` Peter De Schrijver
2018-12-05 6:20 ` Joseph Lo
2018-12-05 6:51 ` Joseph Lo
2018-12-05 9:11 ` Peter De Schrijver
2018-12-05 9:30 ` Joseph Lo
2018-12-07 14:34 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 09/19] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-07 14:39 ` Jon Hunter
2018-12-11 7:34 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 10/19] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-07 14:40 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 11/19] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-07 14:49 ` Jon Hunter
2018-12-11 8:48 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 12/19] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-04 9:30 ` Viresh Kumar
2018-12-04 11:22 ` Dmitry Osipenko
2018-12-05 3:25 ` Joseph Lo
2018-12-07 14:50 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 13/19] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 14/19] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-07 14:54 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 15/19] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-07 14:55 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 16/19] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-07 14:57 ` Jon Hunter
2018-12-11 8:52 ` Joseph Lo
2018-12-04 9:25 ` [PATCH 17/19] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 18/19] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-07 15:03 ` Jon Hunter
2018-12-04 9:25 ` [PATCH 19/19] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-07 15:04 ` Jon Hunter
2018-12-04 15:10 ` Thierry Reding [this message]
2018-12-05 6:11 ` [PATCH 00/19] Tegra210 DFLL support Joseph Lo
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