From: Weiyi Lu <weiyi.lu@mediatek.com> To: Nicolas Boichat <drinkcat@chromium.org>, Matthias Brugger <matthias.bgg@gmail.com>, Stephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh@kernel.org> Cc: James Liao <jamesjj.liao@mediatek.com>, Fan Chen <fan.chen@mediatek.com>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <srv_heupstream@mediatek.com>, <stable@vger.kernel.org>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [PATCH v3 07/12] clk: mediatek: Add flags support for mtk_gate data Date: Mon, 10 Dec 2018 15:32:35 +0800 Message-ID: <20181210073240.32278-9-weiyi.lu@mediatek.com> (raw) In-Reply-To: <20181210073240.32278-1-weiyi.lu@mediatek.com> On some Mediatek platforms, there are critical clocks of clock gate type. To register clock gate with flags CLK_IS_CRITICAL, we need to add the flags field in mtk_gate data and register APIs. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/mediatek/clk-gate.c | 5 +++-- drivers/clk/mediatek/clk-gate.h | 3 ++- drivers/clk/mediatek/clk-mtk.c | 3 ++- drivers/clk/mediatek/clk-mtk.h | 1 + 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 934bf0e45e26..85daf826619a 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate( int clr_ofs, int sta_ofs, u8 bit, - const struct clk_ops *ops) + const struct clk_ops *ops, + unsigned long flags) { struct mtk_clk_gate *cg; struct clk *clk; @@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate( return ERR_PTR(-ENOMEM); init.name = name; - init.flags = CLK_SET_RATE_PARENT; + init.flags = flags | CLK_SET_RATE_PARENT; init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; init.ops = ops; diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 72ef89b3ad7b..9f766dfe1d57 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate( int clr_ofs, int sta_ofs, u8 bit, - const struct clk_ops *ops); + const struct clk_ops *ops, + unsigned long flags); #endif /* __DRV_CLK_GATE_H */ diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 9c0ae4278a94..35359e5397c7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node, gate->regs->set_ofs, gate->regs->clr_ofs, gate->regs->sta_ofs, - gate->shift, gate->ops); + gate->shift, gate->ops, + gate->flags); if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %ld\n", diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 11b5517903d0..928905496c4b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -158,6 +158,7 @@ struct mtk_gate { const struct mtk_gate_regs *regs; int shift; const struct clk_ops *ops; + unsigned long flags; }; int mtk_clk_register_gates(struct device_node *node, -- 2.18.0
next prev parent reply index Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-10 7:32 [PATCH v3 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 00/12] " Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate Weiyi Lu 2018-12-14 21:57 ` Stephen Boyd 2019-02-01 8:21 ` Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 02/12] clk: mediatek: add new clkmux register API Weiyi Lu 2018-12-10 12:30 ` Nicolas Boichat 2019-02-01 8:22 ` Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu 2018-12-14 22:02 ` Stephen Boyd 2019-02-01 8:22 ` Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu 2018-12-10 12:52 ` Nicolas Boichat 2018-12-10 7:32 ` [PATCH v3 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu 2018-12-14 21:57 ` Stephen Boyd 2018-12-10 7:32 ` [PATCH v3 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu 2018-12-10 7:32 ` Weiyi Lu [this message] 2018-12-10 7:32 ` [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu 2018-12-11 1:00 ` Nicolas Boichat 2019-02-01 8:22 ` Weiyi Lu 2018-12-14 21:59 ` Stephen Boyd 2019-02-01 8:22 ` Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu 2018-12-10 7:32 ` [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu 2018-12-14 22:01 ` Stephen Boyd 2019-02-01 8:22 ` Weiyi Lu
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