From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Michael Trimarchi <michael@amarulasolutions.com>,
linux-sunxi <linux-sunxi@googlegroups.com>,
linux-amarula@amarulasolutions.com,
Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH v5 02/17] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk
Date: Mon, 10 Dec 2018 21:47:14 +0530 [thread overview]
Message-ID: <20181210161729.29720-3-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20181210161729.29720-1-jagan@amarulasolutions.com>
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39 ++++++++++++++++++--------
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 5 ++++
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index e3b34a345546..561de393ea23 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -10,6 +10,7 @@
#include <linux/component.h>
#include <linux/crc-ccitt.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
@@ -981,6 +982,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
dsi->host.ops = &sun6i_dsi_host_ops;
dsi->host.dev = dev;
+ dsi->variant = of_device_get_match_data(dev);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base)) {
@@ -1001,17 +1004,20 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
return PTR_ERR(dsi->reset);
}
- dsi->mod_clk = devm_clk_get(dev, "mod");
- if (IS_ERR(dsi->mod_clk)) {
- dev_err(dev, "Couldn't get the DSI mod clock\n");
- return PTR_ERR(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk) {
+ dsi->mod_clk = devm_clk_get(dev, "mod");
+ if (IS_ERR(dsi->mod_clk)) {
+ dev_err(dev, "Couldn't get the DSI mod clock\n");
+ return PTR_ERR(dsi->mod_clk);
+ }
}
/*
* In order to operate properly, that clock seems to be always
* set to 297MHz.
*/
- clk_set_rate_exclusive(dsi->mod_clk, 297000000);
+ if (dsi->variant->has_mod_clk)
+ clk_set_rate_exclusive(dsi->mod_clk, 297000000);
dphy_node = of_parse_phandle(dev->of_node, "phys", 0);
ret = sun6i_dphy_probe(dsi, dphy_node);
@@ -1043,7 +1049,8 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
sun6i_dphy_remove(dsi);
err_unprotect_clk:
- clk_rate_exclusive_put(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_rate_exclusive_put(dsi->mod_clk);
return ret;
}
@@ -1056,7 +1063,8 @@ static int sun6i_dsi_remove(struct platform_device *pdev)
mipi_dsi_host_unregister(&dsi->host);
pm_runtime_disable(dev);
sun6i_dphy_remove(dsi);
- clk_rate_exclusive_put(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_rate_exclusive_put(dsi->mod_clk);
return 0;
}
@@ -1066,7 +1074,8 @@ static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
reset_control_deassert(dsi->reset);
- clk_prepare_enable(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_prepare_enable(dsi->mod_clk);
/*
* Enable the DSI block.
@@ -1094,7 +1103,8 @@ static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
{
struct sun6i_dsi *dsi = dev_get_drvdata(dev);
- clk_disable_unprepare(dsi->mod_clk);
+ if (dsi->variant->has_mod_clk)
+ clk_disable_unprepare(dsi->mod_clk);
reset_control_assert(dsi->reset);
return 0;
@@ -1106,9 +1116,16 @@ static const struct dev_pm_ops sun6i_dsi_pm_ops = {
NULL)
};
+static const struct sun6i_dsi_variant sun6i_a31_dsi = {
+ .has_mod_clk = true,
+};
+
static const struct of_device_id sun6i_dsi_of_table[] = {
- { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
- { }
+ {
+ .compatible = "allwinner,sun6i-a31-mipi-dsi",
+ .data = &sun6i_a31_dsi,
+ },
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index dbbc5b3ecbda..597b62227019 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -20,6 +20,10 @@ struct sun6i_dphy {
struct reset_control *reset;
};
+struct sun6i_dsi_variant {
+ bool has_mod_clk;
+};
+
struct sun6i_dsi {
struct drm_connector connector;
struct drm_encoder encoder;
@@ -35,6 +39,7 @@ struct sun6i_dsi {
struct sun4i_drv *drv;
struct mipi_dsi_device *device;
struct drm_panel *panel;
+ const struct sun6i_dsi_variant *variant;
};
static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
--
2.18.0.321.gffc6fa0e3
next prev parent reply other threads:[~2018-12-10 16:17 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-10 16:17 [PATCH v5 00/17] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2018-12-10 16:17 ` [PATCH v5 01/17] clk: sunxi-ng: Add check for minimal rate to NKM PLLs Jagan Teki
2018-12-10 16:17 ` Jagan Teki [this message]
2018-12-10 16:17 ` [PATCH v5 03/17] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
2018-12-10 16:17 ` [PATCH v5 04/17] dt-bindings: sun6i-dsi: Add compatible for A64 MIPI DSI Jagan Teki
2018-12-10 16:17 ` [PATCH v5 05/17] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer Jagan Teki
2018-12-10 16:17 ` [PATCH v5 06/17] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits Jagan Teki
2018-12-10 16:17 ` [PATCH v5 07/17] drm/sun4i: sun6i_mipi_dsi: Refactor vertical video start delay Jagan Teki
2018-12-11 16:49 ` Maxime Ripard
2018-12-11 17:00 ` Jagan Teki
2018-12-12 19:43 ` Jagan Teki
2018-12-19 15:50 ` Maxime Ripard
2018-12-20 20:56 ` Jagan Teki
2019-01-06 16:29 ` Jagan Teki
2019-01-07 14:11 ` Maxime Ripard
2019-01-07 15:18 ` Jagan Teki
2019-01-08 8:58 ` Maxime Ripard
[not found] ` <CAMty3ZC9OQtwT-iH=S1LhHsBPc_jFKGAnCYYeR9nuKuDWSKLQw@mail.gmail.com>
2019-01-12 16:43 ` Maxime Ripard
2019-01-12 19:37 ` Jagan Teki
2019-01-16 19:17 ` Maxime Ripard
2019-01-17 4:32 ` Jagan Teki
2019-01-18 15:44 ` Jagan Teki
2019-01-22 11:11 ` Maxime Ripard
2019-01-22 11:51 ` Jagan Teki
2019-01-25 21:21 ` Maxime Ripard
2019-01-22 11:14 ` Maxime Ripard
2018-12-10 16:17 ` [PATCH v5 08/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value Jagan Teki
2018-12-10 16:17 ` [PATCH v5 09/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hblk timing calculation Jagan Teki
2018-12-10 16:17 ` [PATCH v5 10/17] drm/sun4i: sun6i_mipi_dsi: Add DSI hblk packet overhead Jagan Teki
2018-12-10 16:17 ` [PATCH v5 11/17] drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp timing value Jagan Teki
2018-12-10 16:17 ` [PATCH v5 12/17] drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation Jagan Teki
2018-12-10 16:17 ` [PATCH v5 13/17] drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator Jagan Teki
2018-12-10 16:17 ` [PATCH v5 14/17] dt-bindings: sun6i-dsi: Add VCC-DSI supply property Jagan Teki
2018-12-10 16:17 ` [PATCH v5 15/17] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI Jagan Teki
2018-12-11 16:32 ` Maxime Ripard
2018-12-11 16:35 ` [linux-sunxi] " Jagan Teki
2018-12-11 16:50 ` Maxime Ripard
2018-12-10 16:17 ` [PATCH v5 16/17] dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) Jagan Teki
2018-12-10 16:17 ` [PATCH v5 17/17] arm64: dts: allwinner: a64: Add DSI pipeline Jagan Teki
2018-12-11 16:34 ` Maxime Ripard
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