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From:   Joseph Lo <josephl@nvidia.com>
To:     Thierry Reding <thierry.reding@gmail.com>,
        Peter De Schrijver <pdeschrijver@nvidia.com>,
        Jonathan Hunter <jonathanh@nvidia.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        Joseph Lo <josephl@nvidia.com>
Subject: [PATCH V2 09/21] clk: tegra: dfll: add protection for find_vdd_map APIs
Date:   Thu, 13 Dec 2018 17:34:26 +0800
Message-ID: <20181213093438.29621-10-josephl@nvidia.com>
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The DFLL hardware supports both I2C and PWM based regulator. SW driver
only touches I2C regulator when generating LUT. And shouldn't touch it
anymore once the DFLL is enabled.

This patch adds the protection for the APIs that only work with I2C mode
to avoid they could be called accidentally.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
*V2:
 - new added patch in V2
---
 drivers/clk/tegra/clk-dfll.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index b3668073d9b4..93cc86f17f7b 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1534,6 +1534,9 @@ static int find_vdd_map_entry_exact(struct tegra_dfll=
 *td, int uV)
 {
 	int i, n_voltages, reg_volt_id, align_step;
=20
+	if (WARN_ON(td->pmu_if =3D=3D TEGRA_DFLL_PMU_PWM))
+		return -EINVAL;
+
 	align_step =3D uV / td->soc->alignment.step_uv;
 	n_voltages =3D regulator_count_voltages(td->vdd_reg);
 	for (i =3D 0; i < n_voltages; i++) {
@@ -1558,6 +1561,9 @@ static int find_vdd_map_entry_min(struct tegra_dfll *=
td, int uV)
 {
 	int i, n_voltages, reg_volt_id, align_step;
=20
+	if (WARN_ON(td->pmu_if =3D=3D TEGRA_DFLL_PMU_PWM))
+		return -EINVAL;
+
 	align_step =3D uV / td->soc->alignment.step_uv;
 	n_voltages =3D regulator_count_voltages(td->vdd_reg);
 	for (i =3D 0; i < n_voltages; i++) {
--=20
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