This series is based on v4.20-rc1. Basically, this series is for the 3rd ECO design change of MT2712.
This series is based on v4.20-rc1. Basically, this series is for the 3rd ECO design change of MT2712. Weiyi Lu (2): dt-bindings: clock: add clock for MT2712 clk: mediatek: update clock driver of MT2712 drivers/clk/mediatek/clk-mt2712.c | 8 ++++++-- include/dt-bindings/clock/mt2712-clk.h | 3 ++- 2 files changed, 8 insertions(+), 3 deletions(-) -- 2.18.0
Add new clock according to 3rd ECO design change. It's the parent clock of audio clock mux. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- include/dt-bindings/clock/mt2712-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h index 76265836a1e1..c3b29dff9c0e 100644 --- a/include/dt-bindings/clock/mt2712-clk.h +++ b/include/dt-bindings/clock/mt2712-clk.h @@ -228,7 +228,8 @@ #define CLK_TOP_NFI2X_EN 189 #define CLK_TOP_NFIECC_EN 190 #define CLK_TOP_NFI1X_CK_EN 191 -#define CLK_TOP_NR_CLK 192 +#define CLK_TOP_APLL2_D3 192 +#define CLK_TOP_NR_CLK 193 /* INFRACFG */ -- 2.18.0
According to 3rd ECO design change, 1. Add new fixed factor clock of audio. 2. Add the parent clocks for audio clock mux. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/mediatek/clk-mt2712.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 991d4093726e..e36f4aab634d 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = { 4), FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, + 3), }; static const char * const axi_parents[] = { @@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = { "apll1_ck", "apll1_d2", "apll1_d4", - "apll1_d8" + "apll1_d8", + "apll1_d3" }; static const char * const a2sys_hp_parents[] = { @@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = { "apll2_ck", "apll2_d2", "apll2_d4", - "apll2_d8" + "apll2_d8", + "apll2_d3" }; static const char * const asm_l_parents[] = { -- 2.18.0
On Fri, 14 Dec 2018 10:04:16 +0800, Weiyi Lu wrote:
> Add new clock according to 3rd ECO design change.
> It's the parent clock of audio clock mux.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> include/dt-bindings/clock/mt2712-clk.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
Quoting Weiyi Lu (2018-12-13 18:04:16)
> Add new clock according to 3rd ECO design change.
> It's the parent clock of audio clock mux.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
Applied to clk-next
Quoting Weiyi Lu (2018-12-13 18:04:17)
> According to 3rd ECO design change,
> 1. Add new fixed factor clock of audio.
> 2. Add the parent clocks for audio clock mux.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
Applied to clk-next