From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDBDFC43387 for ; Sat, 15 Dec 2018 10:36:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 71DF42084D for ; Sat, 15 Dec 2018 10:36:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="PLOCedwF"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="cjJBjX2a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730084AbeLOKgk (ORCPT ); Sat, 15 Dec 2018 05:36:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:45786 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729671AbeLOKgj (ORCPT ); Sat, 15 Dec 2018 05:36:39 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id EBB11607DF; Sat, 15 Dec 2018 10:36:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1544870197; bh=yL7wA2IXXoPSHlHbyWOxsA29820L7QP0xYN2yZNCC8k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PLOCedwFbDVWNiOT7XyYn6DnUHLjxHrwukRj0c97ARZK5KoYkvOK89MRJyHx9pZi1 fPltyGxDRM6BF5iLxbifxvbyH6AE5drJYNg7eI57gvbDriLFnmkunp9izJtHvo94z8 DXjRn22Zbi/ZFPwyOnc+5GW2Js37ktFLGXLOQAFo= Received: from govinds-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: govinds@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2064B608CF; Sat, 15 Dec 2018 10:36:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1544870193; bh=yL7wA2IXXoPSHlHbyWOxsA29820L7QP0xYN2yZNCC8k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cjJBjX2ahNynQAcVW32+VXg2RKQOfN583wJ0Qa/G0gspf3Q0CYmMbJwbfrADVLZX2 +ZqjvYc2qH1fXU8VpcVMEsGiFnsMpwXkcQGNBZwrQ/xbbimBntKn7Hk/xFnGnhP8MI bBbXiHEpiyTkElHB0OzYROzhgwNaOmHileFjAMXg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2064B608CF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=govinds@codeaurora.org From: Govind Singh To: bjorn.andersson@linaro.org, linux-remoteproc@vger.kernel.org, sboyd@kernel.org Cc: linux-clk@vger.kernel.org, sricharan@codeaurora.org, sibis@codeaurora.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, david.brown@linaro.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, Govind Singh Subject: [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Date: Sat, 15 Dec 2018 16:05:56 +0530 Message-Id: <20181215103557.2748-7-govinds@codeaurora.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181215103557.2748-1-govinds@codeaurora.org> References: <20181215103557.2748-1-govinds@codeaurora.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS). Signed-off-by: Govind Singh --- .../bindings/remoteproc/qcom,q6v5.txt | 61 ++ drivers/remoteproc/qcom_q6v5_wcss.c | 544 +++++++++++++++++- 2 files changed, 577 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 9ff5b0309417..9372dedcd7e2 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -13,6 +13,7 @@ on the Qualcomm Hexagon core. "qcom,msm8974-mss-pil" "qcom,msm8996-mss-pil" "qcom,sdm845-mss-pil" + "qcom,qcs404-wcss-pil" - reg: Usage: required @@ -153,3 +154,63 @@ Hexagon, as it is found on MSM8974 boards. memory-region = <&mpss_region>; }; }; + + remoteproc-wcss { + compatible = "qcom,qcs404-wcss-pil"; + reg = <0x07400000 0x00104>, <0x07500000 0x4e000>; + reg-names = "qdsp6", "q6stop"; + + interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>, + <&gcc GCC_WCSS_Q6_AHB_CBCR_CLK>, + <&gcc GCC_WCSS_Q6_AXIM_CBCR_CLK>, + + <&clock_wcsscc WCSS_AHBFABRIC_CBCR_CLK>, + <&clock_wcsscc WCSS_LCC_CBCR_CLK>, + <&clock_wcsscc WCSS_AHBS_CBCR_CLK>, + <&clock_wcsscc WCSS_TCM_CBCR_CLK>, + <&clock_wcsscc WCSS_AHBM_CBCR_CLK>, + <&clock_wcsscc WCSS_AXIM_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_XO_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_SLEEP_CBCR_CLK>, + <&clock_wcsscc WCSS_QDSP6SS_GFMMUX_CLK>, + <&clock_wcsscc WCSS_BCR_CBCR_CLK>; + + clock-names = "xo", "gcc_abhs_cbcr", "gcc_axim_cbcr", + "wcss_ahbfabric_cbcr", "wcnss_csr_cbcr", + "wcnss_ahbs_cbcr", "wcnss_tcm_slave_cbcr", + "wcnss_abhm_cbcr", "wcnss_axim_cbcr", + "wcnss_qdsp6ss_xo_cbcr", "wcnss_sleep_cbcr", + "wcnss_core_gfm", "wcss_bcr_cbcr"; + resets = <&gcc GCC_WDSP_RESTART>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_RESET>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_CORE_RESET>, + <&clock_wcsscc Q6SSTOP_QDSP6SS_BUS_RESET>, + <&clock_wcsscc Q6SSTOP_BCR_RESET>; + reset-names = "wcss_reset", "wcss_q6_reset", + "wcss_q6_core_reset", "wcss_q6_bus_reset", + "wcss_q6_bcr_reset"; + + memory-region = <&wlan_fw_mem>; + + qcom,smem-states = <&wcss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + qcom,halt-regs = <&tcsr_wlan_q6 0x18000>; + glink-edge { + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 16>; + + label = "wcss"; + }; + }; + diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 129f82404656..3f66bd8fa407 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -4,14 +4,19 @@ * Copyright (C) 2014 Sony Mobile Communications AB * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. */ +#include +#include +#include #include #include #include #include +#include #include #include #include #include +#include #include #include #include "qcom_common.h" @@ -23,6 +28,9 @@ #define Q6SS_GFMUX_CTL_REG 0x020 #define Q6SS_PWR_CTL_REG 0x030 #define Q6SS_MEM_PWR_CTL 0x0B0 +#define Q6SS_STRAP_ACC 0x110 +#define Q6SS_CGC_OVERRIDE 0x034 +#define Q6SS_BCR_REG 0x6000 /* AXI Halt Register Offsets */ #define AXI_HALTREQ_REG 0x0 @@ -36,6 +44,9 @@ #define Q6SS_CORE_ARES BIT(1) #define Q6SS_BUS_ARES_ENABLE BIT(2) +/* Q6SS_BRC_RESET */ +#define Q6SS_BRC_BLK_ARES BIT(0) + /* Q6SS_GFMUX_CTL */ #define Q6SS_CLK_ENABLE BIT(1) @@ -44,6 +55,7 @@ #define Q6SS_SLP_RET_N BIT(19) #define Q6SS_CLAMP_IO BIT(20) #define QDSS_BHS_ON BIT(21) +#define QDSS_Q6_MEMORIES GENMASK(15, 0) /* Q6SS parameters */ #define Q6SS_LDO_BYP BIT(25) @@ -70,12 +82,22 @@ #define TCSR_WCSS_CLK_MASK 0x1F #define TCSR_WCSS_CLK_ENABLE 0x14 +#define MAX_HALT_REG 3 +enum { + WCSS_IPQ8074, + WCSS_QCS404, +}; + struct wcss_data { - void (*pas_handover)(struct qcom_q6v5 *q6v5); const char *firmware_name; int crash_reason_smem; int version; - int pas_id; + bool aon_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; + const struct rproc_ops *ops; + void (*pas_handover)(struct qcom_q6v5 *q6v5); }; struct q6v5_wcss { @@ -83,12 +105,32 @@ struct q6v5_wcss { void __iomem *reg_base; void __iomem *rmb_base; + void __iomem *q6stop_base; struct regmap *halt_map; u32 halt_q6; u32 halt_wcss; u32 halt_nc; + struct clk *xo; + struct clk *ahbfabric_cbcr_clk; + struct clk *gcc_abhs_cbcr; + struct clk *gcc_axim_cbcr; + struct clk *lcc_csr_cbcr; + struct clk *ahbs_cbcr; + struct clk *tcm_slave_cbcr; + struct clk *qdsp6ss_abhm_cbcr; + struct clk *qdsp6ss_sleep_cbcr; + struct clk *qdsp6ss_axim_cbcr; + struct clk *qdsp6ss_xo_cbcr; + struct clk *qdsp6ss_core_gfmux; + struct clk *wcss_bcr_cbcr; + struct regulator *cx_supply; + + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_sysmon *sysmon; + struct reset_control *wcss_aon_reset; struct reset_control *wcss_reset; struct reset_control *wcss_q6_reset; @@ -99,9 +141,7 @@ struct q6v5_wcss { phys_addr_t mem_reloc; void *mem_region; size_t mem_size; - int crash_reason_smem; - int pas_id; int version; }; @@ -245,6 +285,197 @@ static int q6v5_wcss_start(struct rproc *rproc) return ret; } +static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss) +{ + unsigned long val; + int ret, idx; + + /* Toggle the restart */ + reset_control_assert(wcss->wcss_reset); + usleep_range(200, 300); + reset_control_deassert(wcss->wcss_reset); + usleep_range(200, 300); + + /* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ + ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); + if (ret) + return ret; + + /* Remove reset to the WCNSS QDSP6SS */ + val = readl(wcss->q6stop_base + Q6SS_BCR_REG); + val &= ~Q6SS_BRC_BLK_ARES; + writel(val, wcss->q6stop_base + Q6SS_BCR_REG); + + /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ + ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); + if (ret) + goto disable_gcc_abhs_cbcr_clk; + + /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ + ret = clk_prepare_enable(wcss->lcc_csr_cbcr); + if (ret) + goto disable_ahbfabric_cbcr_clk; + + /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ + ret = clk_prepare_enable(wcss->ahbs_cbcr); + if (ret) + goto disable_csr_cbcr_clk; + + /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ + ret = clk_prepare_enable(wcss->tcm_slave_cbcr); + if (ret) + goto disable_ahbs_cbcr_clk; + + /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ + ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); + if (ret) + goto disable_tcm_slave_cbcr_clk; + + /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ + ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); + if (ret) + goto disable_abhm_cbcr_clk; + + /* Enable the Q6SS XO CBC */ + ret = clk_prepare_enable(wcss->qdsp6ss_xo_cbcr); + if (ret) + goto disable_axim_cbcr_clk; + + writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); + + /* Enable QDSP6 sleep clock clock */ + ret = clk_prepare_enable(wcss->qdsp6ss_sleep_cbcr); + if (ret) + goto disable_xo_cbcr_clk; + + /* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ + ret = clk_prepare_enable(wcss->gcc_axim_cbcr); + if (ret) + goto disable_sleep_cbcr_clk; + + /* Assert resets, stop core */ + val = readl(wcss->reg_base + Q6SS_RESET_REG); + val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; + writel(val, wcss->reg_base + Q6SS_RESET_REG); + + /* Program the QDSP6SS PWR_CTL register */ + writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); + + writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); + + writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); + + writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); + + /* + * Enable memories by turning on the QDSP6 memory foot/head switch, one + * bank at a time to avoid in-rush current + */ + for (idx = 28; idx >= 0; idx--) { + writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | + (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); + } + + writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); + writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); + + val = readl(wcss->reg_base + Q6SS_RESET_REG); + val &= ~Q6SS_CORE_ARES; + writel(val, wcss->reg_base + Q6SS_RESET_REG); + + /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ + ret = clk_prepare_enable(wcss->qdsp6ss_core_gfmux); + if (ret) + goto disable_gcc_axim_cbcr_clk; + + /* Enable sleep clock branch needed for BCR circuit */ + ret = clk_prepare_enable(wcss->wcss_bcr_cbcr); + if (ret) + goto disable_core_gfmux_clk; + + return 0; + +disable_core_gfmux_clk: + clk_disable_unprepare(wcss->qdsp6ss_core_gfmux); +disable_gcc_axim_cbcr_clk: + clk_disable_unprepare(wcss->gcc_axim_cbcr); +disable_sleep_cbcr_clk: + clk_disable_unprepare(wcss->qdsp6ss_sleep_cbcr); +disable_xo_cbcr_clk: + clk_disable_unprepare(wcss->qdsp6ss_xo_cbcr); +disable_axim_cbcr_clk: + clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); +disable_abhm_cbcr_clk: + clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); +disable_tcm_slave_cbcr_clk: + clk_disable_unprepare(wcss->tcm_slave_cbcr); +disable_ahbs_cbcr_clk: + clk_disable_unprepare(wcss->ahbs_cbcr); +disable_csr_cbcr_clk: + clk_disable_unprepare(wcss->lcc_csr_cbcr); +disable_ahbfabric_cbcr_clk: + clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); +disable_gcc_abhs_cbcr_clk: + clk_disable_unprepare(wcss->gcc_abhs_cbcr); + + return ret; +} + +static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss) +{ + unsigned long val; + + writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); + + /* Start core execution */ + val = readl(wcss->reg_base + Q6SS_RESET_REG); + val &= ~Q6SS_STOP_CORE; + writel(val, wcss->reg_base + Q6SS_RESET_REG); + + return 0; +} + +static int q6v5_qcs404_wcss_start(struct rproc *rproc) +{ + struct q6v5_wcss *wcss = rproc->priv; + int ret; + + ret = clk_prepare_enable(wcss->xo); + if (ret) + return ret; + + ret = regulator_enable(wcss->cx_supply); + if (ret) + goto disable_xo_clk; + + qcom_q6v5_prepare(&wcss->q6v5); + + ret = q6v5_wcss_qcs404_power_on(wcss); + if (ret) { + dev_err(wcss->dev, "wcss clk_enable failed\n"); + goto disable_cx_supply; + } + + writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); + + q6v5_wcss_qcs404_reset(wcss); + + ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); + if (ret == -ETIMEDOUT) { + dev_err(wcss->dev, "start timed out\n"); + goto disable_cx_supply; + } + + return 0; + +disable_cx_supply: + regulator_disable(wcss->cx_supply); +disable_xo_clk: + clk_disable_unprepare(wcss->xo); + + return ret; +} + static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, struct regmap *halt_map, u32 offset) @@ -279,6 +510,58 @@ static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); } +static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss) +{ + unsigned long val; + int ret; + + q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); + + /* assert clamps to avoid MX current inrush */ + val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); + val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM); + writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); + + /* Disable memories by turning off memory foot/headswitch */ + writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & + ~QDSS_Q6_MEMORIES), + wcss->reg_base + Q6SS_MEM_PWR_CTL); + + /* Clear the BHS_ON bit */ + val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); + val &= ~Q6SS_BHS_ON; + writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); + + clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); + clk_disable_unprepare(wcss->lcc_csr_cbcr); + clk_disable_unprepare(wcss->tcm_slave_cbcr); + clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); + clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); + clk_disable_unprepare(wcss->qdsp6ss_xo_cbcr); + clk_disable_unprepare(wcss->ahbs_cbcr); + clk_disable_unprepare(wcss->wcss_bcr_cbcr); + clk_disable_unprepare(wcss->qdsp6ss_core_gfmux); + clk_disable_unprepare(wcss->gcc_abhs_cbcr); + + ret = reset_control_assert(wcss->wcss_reset); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + usleep_range(200, 300); + + ret = reset_control_deassert(wcss->wcss_reset); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + usleep_range(200, 300); + + clk_disable_unprepare(wcss->gcc_axim_cbcr); + + return 0; +} + static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) { int ret; @@ -392,6 +675,14 @@ static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) return 0; } +static void q6v5_wcss_handover(struct qcom_q6v5 *q6v5) +{ + struct q6v5_wcss *wcss = container_of(q6v5, struct q6v5_wcss, q6v5); + + regulator_disable(wcss->cx_supply); + clk_disable_unprepare(wcss->xo); +} + static int q6v5_wcss_stop(struct rproc *rproc) { struct q6v5_wcss *wcss = rproc->priv; @@ -404,7 +695,11 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } - ret = q6v5_wcss_powerdown(wcss); + if (wcss->version == WCSS_QCS404) + ret = q6v5_qcs404_wcss_shutdown(wcss); + else + ret = q6v5_wcss_powerdown(wcss); + if (ret) return ret; @@ -447,14 +742,25 @@ static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .get_boot_addr = rproc_elf_get_boot_addr, }; -static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) +static const struct rproc_ops q6v5_wcss_qcs404_ops = { + .start = q6v5_qcs404_wcss_start, + .stop = q6v5_wcss_stop, + .da_to_va = q6v5_wcss_da_to_va, + .load = q6v5_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, +}; + +static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, + bool aon_reset_required) { struct device *dev = wcss->dev; - wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); - if (IS_ERR(wcss->wcss_aon_reset)) { - dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n"); - return PTR_ERR(wcss->wcss_aon_reset); + if (aon_reset_required) { + wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset"); + if (IS_ERR(wcss->wcss_aon_reset)) { + dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); + return PTR_ERR(wcss->wcss_aon_reset); + } } wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset"); @@ -475,35 +781,60 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss) static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, struct platform_device *pdev) { - struct of_phandle_args args; + unsigned int halt_reg[MAX_HALT_REG] = {0}; + struct device_node *syscon; struct resource *res; int ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); - wcss->reg_base = devm_ioremap_resource(&pdev->dev, res); + wcss->reg_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); if (IS_ERR(wcss->reg_base)) return PTR_ERR(wcss->reg_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); - wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(wcss->rmb_base)) - return PTR_ERR(wcss->rmb_base); + if (wcss->version == WCSS_QCS404) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "q6stop"); + if (!res) { + dev_err(&pdev->dev, "invalid q6stop_base resource\n"); + return -EINVAL; + } + + wcss->q6stop_base = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (IS_ERR(wcss->q6stop_base)) + return PTR_ERR(wcss->q6stop_base); + } else { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); + wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(wcss->rmb_base)) + return PTR_ERR(wcss->rmb_base); + } - ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, - "qcom,halt-regs", 3, 0, &args); - if (ret < 0) { + syscon = of_parse_phandle(pdev->dev.of_node, + "qcom,halt-regs", 0); + if (!syscon) { dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); return -EINVAL; } - wcss->halt_map = syscon_node_to_regmap(args.np); - of_node_put(args.np); + wcss->halt_map = syscon_node_to_regmap(syscon); + of_node_put(syscon); if (IS_ERR(wcss->halt_map)) return PTR_ERR(wcss->halt_map); - wcss->halt_q6 = args.args[0]; - wcss->halt_wcss = args.args[1]; - wcss->halt_nc = args.args[2]; + ret = of_property_read_variable_u32_array(pdev->dev.of_node, + "qcom,halt-regs", + halt_reg, 0, + MAX_HALT_REG); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); + return -EINVAL; + } + + wcss->halt_q6 = halt_reg[0]; + wcss->halt_wcss = halt_reg[1]; + wcss->halt_nc = halt_reg[2]; return 0; } @@ -537,6 +868,132 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) return 0; } +static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) +{ + int ret; + + wcss->xo = devm_clk_get(wcss->dev, "xo"); + if (IS_ERR(wcss->xo)) { + ret = PTR_ERR(wcss->xo); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get xo clock"); + return ret; + } + + wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); + if (IS_ERR(wcss->gcc_abhs_cbcr)) { + ret = PTR_ERR(wcss->gcc_abhs_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get gcc_sway clock\n"); + return PTR_ERR(wcss->gcc_abhs_cbcr); + } + + wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); + if (IS_ERR(wcss->gcc_axim_cbcr)) { + ret = PTR_ERR(wcss->gcc_axim_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get csr cbcr clk\n"); + return PTR_ERR(wcss->gcc_axim_cbcr); + } + + wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, + "wcss_ahbfabric_cbcr"); + if (IS_ERR(wcss->ahbfabric_cbcr_clk)) { + ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get gcc_sway clock\n"); + return PTR_ERR(wcss->ahbfabric_cbcr_clk); + } + + wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "wcnss_csr_cbcr"); + if (IS_ERR(wcss->lcc_csr_cbcr)) { + ret = PTR_ERR(wcss->lcc_csr_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get csr cbcr clk\n"); + return PTR_ERR(wcss->lcc_csr_cbcr); + } + + wcss->ahbs_cbcr = devm_clk_get(wcss->dev, + "wcnss_ahbs_cbcr"); + if (IS_ERR(wcss->ahbs_cbcr)) { + ret = PTR_ERR(wcss->ahbs_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); + return PTR_ERR(wcss->ahbs_cbcr); + } + + wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, + "wcnss_tcm_slave_cbcr"); + if (IS_ERR(wcss->tcm_slave_cbcr)) { + ret = PTR_ERR(wcss->tcm_slave_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); + return PTR_ERR(wcss->tcm_slave_cbcr); + } + + wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "wcnss_abhm_cbcr"); + if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) { + ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); + return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); + } + + wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "wcnss_axim_cbcr"); + if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) { + ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); + return PTR_ERR(wcss->qdsp6ss_abhm_cbcr); + } + + wcss->qdsp6ss_sleep_cbcr = devm_clk_get(wcss->dev, "wcnss_sleep_cbcr"); + if (IS_ERR(wcss->qdsp6ss_sleep_cbcr)) { + ret = PTR_ERR(wcss->qdsp6ss_sleep_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get qdsp6ss_sleep clk\n"); + return PTR_ERR(wcss->qdsp6ss_sleep_cbcr); + } + + wcss->qdsp6ss_xo_cbcr = devm_clk_get(wcss->dev, + "wcnss_qdsp6ss_xo_cbcr"); + if (IS_ERR(wcss->qdsp6ss_xo_cbcr)) { + ret = PTR_ERR(wcss->qdsp6ss_xo_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get qdsp6ss_xo_cbcr clk\n"); + return PTR_ERR(wcss->qdsp6ss_xo_cbcr); + } + + wcss->qdsp6ss_core_gfmux = devm_clk_get(wcss->dev, "wcnss_core_gfm"); + if (IS_ERR(wcss->qdsp6ss_core_gfmux)) { + ret = PTR_ERR(wcss->qdsp6ss_core_gfmux); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get core gfm clk\n"); + return PTR_ERR(wcss->qdsp6ss_core_gfmux); + } + + wcss->wcss_bcr_cbcr = devm_clk_get(wcss->dev, "wcss_bcr_cbcr"); + if (IS_ERR(wcss->wcss_bcr_cbcr)) { + ret = PTR_ERR(wcss->wcss_bcr_cbcr); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); + return PTR_ERR(wcss->wcss_bcr_cbcr); + } + + return 0; +} + +static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) +{ + wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); + if (IS_ERR(wcss->cx_supply)) + return PTR_ERR(wcss->cx_supply); + + regulator_set_load(wcss->cx_supply, 100000); + + return 0; +} + static int q6v5_wcss_probe(struct platform_device *pdev) { const struct wcss_data *desc; @@ -548,7 +1005,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (!desc) return -EINVAL; - rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, desc->firmware_name, sizeof(*wcss)); if (!rproc) { dev_err(&pdev->dev, "failed to allocate rproc\n"); @@ -557,9 +1014,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; - wcss->pas_id = desc->pas_id; wcss->version = desc->version; - wcss->crash_reason_smem = desc->crash_reason_smem; + + wcss->version = desc->version; ret = q6v5_wcss_init_mmio(wcss, pdev); if (ret) @@ -569,7 +1026,17 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) goto free_rproc; - ret = q6v5_wcss_init_reset(wcss); + if (wcss->version == WCSS_QCS404) { + ret = q6v5_wcss_init_clock(wcss); + if (ret) + goto free_rproc; + + ret = q6v5_wcss_init_regulator(wcss); + if (ret) + goto free_rproc; + } + + ret = q6v5_wcss_init_reset(wcss, desc->aon_reset_required); if (ret) goto free_rproc; @@ -578,6 +1045,12 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) goto free_rproc; + qcom_add_glink_subdev(rproc, &wcss->glink_subdev); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name); + wcss->sysmon = qcom_add_sysmon_subdev(rproc, + desc->sysmon_name, + desc->ssctl_id); + ret = rproc_add(rproc); if (ret) goto free_rproc; @@ -605,11 +1078,26 @@ static int q6v5_wcss_remove(struct platform_device *pdev) static const struct wcss_data wcss_ipq8074_res_init = { .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = 421, + .aon_reset_required = true, .pas_handover = NULL, + .ops = &q6v5_wcss_ipq8074_ops, +}; + +static const struct wcss_data wcss_qcs404_res_init = { + .crash_reason_smem = 421, + .firmware_name = "wcnss.mdt", + .version = WCSS_QCS404, + .aon_reset_required = false, + .ssr_name = "mpss", + .sysmon_name = "wcnss", + .ssctl_id = 0x12, + .ops = &q6v5_wcss_qcs404_ops, + .pas_handover = q6v5_wcss_handover, }; static const struct of_device_id q6v5_wcss_of_match[] = { { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init }, + { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init }, { }, }; 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