* [PATCH 0/2] mmp2: separate LCDC peripheral clk form the display
@ 2019-01-21 6:31 Lubomir Rintel
2019-01-21 6:31 ` [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
2019-01-21 6:31 ` [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock Lubomir Rintel
0 siblings, 2 replies; 6+ messages in thread
From: Lubomir Rintel @ 2019-01-21 6:31 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree
Hi,
this pair of patches fix how the display clocks are configured on the
MMP2 platform.
The dt-bindings patch assumes the SP clock is not there as it probably
was a mistake to expose it (see the 'Revert "dt-bindings: marvell,mmp2:
Add clock id for the SP clock' patch sent separately).
Thanks,
Lubo
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
2019-01-21 6:31 [PATCH 0/2] mmp2: separate LCDC peripheral clk form the display Lubomir Rintel
@ 2019-01-21 6:31 ` Lubomir Rintel
2019-02-21 21:53 ` Stephen Boyd
2019-01-21 6:31 ` [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock Lubomir Rintel
1 sibling, 1 reply; 6+ messages in thread
From: Lubomir Rintel @ 2019-01-21 6:31 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree,
Lubomir Rintel
The peripheral clock is required for access the the LCDC registers. It
is in fact separate from the "AXI clock" that is optionally used to
generate the pixel clock and as such requires a separate clock id.
Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
include/dt-bindings/clock/marvell,mmp2.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index 228a5e234af0..e785c6eb3561 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -71,6 +71,7 @@
#define MMP2_CLK_CCIC1_MIX 117
#define MMP2_CLK_CCIC1_PHY 118
#define MMP2_CLK_CCIC1_SPHY 119
+#define MMP2_CLK_DISP0_LCDC 120
#define MMP2_NR_CLKS 200
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock
2019-01-21 6:31 [PATCH 0/2] mmp2: separate LCDC peripheral clk form the display Lubomir Rintel
2019-01-21 6:31 ` [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
@ 2019-01-21 6:31 ` Lubomir Rintel
2019-02-21 21:53 ` Stephen Boyd
1 sibling, 1 reply; 6+ messages in thread
From: Lubomir Rintel @ 2019-01-21 6:31 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree,
Lubomir Rintel
These are in fact two clocks, they shouldn't be exposed as one. One is
required for accessing LCD controller registers (peripheral clock), while
other (AXI clock) can be optionally used as a pixel clock source for the
panel.
LCDC can alternatively use different clocks than the Display 1 AXI clock
for generating the pixel clock: the second AXI clock (fixed in this
commit too), the HDMI PLL, or the AXI bus clock.
They should really be controlled independently.
Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index d083b860f083..a60a1be937ad 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -229,9 +229,10 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = {
{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
{MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
{MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
- {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+ {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
+ {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
- {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
+ {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
2019-01-21 6:31 ` [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
@ 2019-02-21 21:53 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-21 21:53 UTC (permalink / raw)
To: Lubomir Rintel, Michael Turquette
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree,
Lubomir Rintel
Quoting Lubomir Rintel (2019-01-20 22:31:28)
> The peripheral clock is required for access the the LCDC registers. It
> is in fact separate from the "AXI clock" that is optionally used to
> generate the pixel clock and as such requires a separate clock id.
>
> Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock
2019-01-21 6:31 ` [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock Lubomir Rintel
@ 2019-02-21 21:53 ` Stephen Boyd
0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-21 21:53 UTC (permalink / raw)
To: Lubomir Rintel, Michael Turquette
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree,
Lubomir Rintel
Quoting Lubomir Rintel (2019-01-20 22:31:29)
> These are in fact two clocks, they shouldn't be exposed as one. One is
> required for accessing LCD controller registers (peripheral clock), while
> other (AXI clock) can be optionally used as a pixel clock source for the
> panel.
>
> LCDC can alternatively use different clocks than the Display 1 AXI clock
> for generating the pixel clock: the second AXI clock (fixed in this
> commit too), the HDMI PLL, or the AXI bus clock.
>
> They should really be controlled independently.
>
> Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock
2019-02-11 10:20 [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
@ 2019-02-11 10:20 ` Lubomir Rintel
0 siblings, 0 replies; 6+ messages in thread
From: Lubomir Rintel @ 2019-02-11 10:20 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Rob Herring, Mark Rutland, linux-clk, linux-kernel, devicetree,
Lubomir Rintel
These are in fact two clocks, they shouldn't be exposed as one. One is
required for accessing LCD controller registers (peripheral clock), while
other (AXI clock) can be optionally used as a pixel clock source for the
panel.
LCDC can alternatively use different clocks than the Display 1 AXI clock
for generating the pixel clock: the second AXI clock (fixed in this
commit too), the HDMI PLL, or the AXI bus clock.
They should really be controlled independently.
Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
drivers/clk/mmp/clk-of-mmp2.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
index d083b860f083..a60a1be937ad 100644
--- a/drivers/clk/mmp/clk-of-mmp2.c
+++ b/drivers/clk/mmp/clk-of-mmp2.c
@@ -229,9 +229,10 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = {
{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
{MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
{MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
- {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
+ {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
+ {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
- {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
+ {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
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2019-01-21 6:31 [PATCH 0/2] mmp2: separate LCDC peripheral clk form the display Lubomir Rintel
2019-01-21 6:31 ` [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
2019-02-21 21:53 ` Stephen Boyd
2019-01-21 6:31 ` [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock Lubomir Rintel
2019-02-21 21:53 ` Stephen Boyd
2019-02-11 10:20 [PATCH 1/2] dt-bindings: marvell,mmp2: Add clock id for the LCDC clock Lubomir Rintel
2019-02-11 10:20 ` [PATCH 2/2] clk: mmp2: separate LCDC peripheral clk form the display clock Lubomir Rintel
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