Linux-Clk Archive on lore.kernel.org
 help / color / Atom feed
From: Thierry Reding <thierry.reding@gmail.com>
To: Joseph Lo <josephl@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH V4 00/20] Tegra210 DFLL support
Date: Fri, 25 Jan 2019 14:46:17 +0100
Message-ID: <20190125134617.GE22565@ulmo> (raw)
In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com>

[-- Attachment #1: Type: text/plain, Size: 4183 bytes --]

On Fri, Jan 04, 2019 at 11:06:42AM +0800, Joseph Lo wrote:
> This series introduces support for the DFLL as a CPU clock source
> on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which
> is driven directly by the DFLLs PWM output, we also introduce support
> for PWM regulators next to I2C controlled regulators. The DFLL output
> frequency is directly controlled by the regulator voltage. The registers
> for controlling the PWM are part of the DFLL IP block, so there's no
> separate linux regulator object involved because the regulator IC only
> supplies the rail powering the CPUs. It doesn't have any other controls.
> 
> The patch 1~4 are the patches of DT bindings update for DFLL clock and
> Tegra124 cpufreq, which add PWM and Tegra210 support for DFLL clock and
> remove deprecate properties for Tegra124 cpufreq bindings.
> 
> The patch 5~10 are the patches for DFLL clock driver update for PWM-mode
> DFLL support.
> 
> The patch 11~13 are the Tegra124 cpufreq driver update to make it
> work with Tegra210.
> 
> The patch 14~19 are the devicetree files update for Tegra210 SoC and
> platforms. Two platforms are updated here for different DFLL mode usage.
> The Tegra210-p2371-2180 (a.k.a. Jetson Tx1) uses DFLL-PWM and the
> Tegra210-smaug (a.k.a. Pixel C) uses DFLL-I2C. So two different modes
> are verified with this series.
> 
> The patch 20 is the patch for enabling the CPU regulator for Smaug
> board.
> 
> * Update in V4:
>  - s/nvidia,pwm-period/nvidia,pwm-period-nanoseconds/ in patch 1 for
>  DFLL DT bindings update.
>  - remove parenthesis in Kconfig of DFLL driver
>  - add more ack and RB tags
> 
> * Update in V3:
>  - Squash patch 9 in previous series into patch 7 (ref. [0])
>  - minor fixes in patch 6 for geting alignment data
>  - more variable type fixes in patch 7
>  - fix the error handling in patch 8
>  - collect more ack tags
> 
> * Update in V2:
>  - Add two patches that suggested from comments in V1. See patch 9 and
>  14.
>  - Update DT binding for DFLL-PWM mode in patch 1.
>  - Update the code for how to get regulator data from DT or regulator
>  API in patch 6.
>  - Update to use lut_uv table for LUT lookup in patch 7. That makes the
>  generic lut table to work with both I2C and PWM mode.
>  - not allow Tegra124 cpufreq driver to be built as a module and remove
>  the removal function in patch 12.
> 
> [0]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=81595
> 
> Joseph Lo (17):
>   dt-bindings: clock: tegra124-dfll: add Tegra210 support
>   dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required
>     properties
>   dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required
>     properties
>   clk: tegra: dfll: CVB calculation alignment with the regulator
>   clk: tegra: dfll: support PWM regulator control
>   clk: tegra: dfll: round down voltages based on alignment
>   clk: tegra: dfll: add CVB tables for Tegra210
>   cpufreq: tegra124: do not handle the CPU rail
>   cpufreq: tegra124: extend to support Tegra210
>   cpufreq: dt-platdev: add Tegra210 to blacklist
>   arm64: dts: tegra210: add DFLL clock
>   arm64: dts: tegra210: add CPU clocks
>   arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support
>   arm64: dts: tegra210-p2371-2180: enable DFLL clock
>   arm64: dts: tegra210-smaug: add CPU power rail regulator
>   arm64: dts: tegra210-smaug: enable DFLL clock
>   arm64: defconfig: Enable MAX8973 regulator
> 
> Peter De Schrijver (3):
>   dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM
>     regulator
>   clk: tegra: dfll: registration for multiple SoCs
>   clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210

Joseph,

can you detail the dependencies between the various patches. From a
brief look the CPU frequency driver changes are completely separate
bits and it should be possible to apply them to the cpufreq tree.

The clock changes also seem independent of the rest.

Are there any dependencies at all that we need to be mindful about?
Or can individual maintainers just pick up the subseries directly?

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

  parent reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-04  3:06 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2019-01-08  0:35   ` Joseph Lo
2019-01-11  8:14     ` Joseph Lo
2019-01-11 19:32   ` Rob Herring
2019-01-04  3:06 ` [PATCH V4 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2019-01-04  3:06 ` [PATCH V4 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2019-01-04  3:06 ` [PATCH V4 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2019-01-04  3:06 ` [PATCH V4 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2019-01-04  3:06 ` [PATCH V4 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2019-01-04  3:06 ` [PATCH V4 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2019-01-04  3:06 ` [PATCH V4 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2019-01-08  0:33   ` Joseph Lo
2019-01-09 18:39   ` Stephen Boyd
2019-01-04  3:06 ` [PATCH V4 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2019-01-04  3:06 ` [PATCH V4 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2019-01-04  3:06 ` [PATCH V4 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2019-01-04  3:06 ` [PATCH V4 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2019-01-04  3:06 ` [PATCH V4 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2019-01-04  3:06 ` [PATCH V4 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2019-01-04  3:06 ` [PATCH V4 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2019-01-04  3:07 ` [PATCH V4 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2019-01-04  3:07 ` [PATCH V4 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2019-01-25 13:46 ` Thierry Reding [this message]
2019-01-28  1:43   ` [PATCH V4 00/20] Tegra210 DFLL support Joseph Lo
2019-01-28  7:54     ` Thierry Reding
2019-02-01  2:49       ` Joseph Lo
2019-02-05 22:27         ` Stephen Boyd

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190125134617.GE22565@ulmo \
    --to=thierry.reding@gmail.com \
    --cc=jonathanh@nvidia.com \
    --cc=josephl@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=pdeschrijver@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-Clk Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-clk/0 linux-clk/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-clk linux-clk/ https://lore.kernel.org/linux-clk \
		linux-clk@vger.kernel.org linux-clk@archiver.kernel.org
	public-inbox-index linux-clk


Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-clk


AGPL code for this site: git clone https://public-inbox.org/ public-inbox