From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Sasha Levin <sashal@kernel.org>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org
Subject: [PATCH AUTOSEL 4.19 061/258] clk: meson: meson8b: fix the width of the cpu_scale_div clock
Date: Mon, 28 Jan 2019 10:56:07 -0500 [thread overview]
Message-ID: <20190128155924.51521-61-sashal@kernel.org> (raw)
In-Reply-To: <20190128155924.51521-1-sashal@kernel.org>
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[ Upstream commit a8662eadd1032018f31e37deda811790b2326662 ]
According to the public S805 datasheet HHI_SYS_CPU_CLK_CNTL1[29:20] is
the register for the CPU scale_div clock. This matches the code in
Amlogic's 3.10 GPL kernel sources:
N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF;
This means that the divider register is 10 bit wide instead of 9 bits.
So far this is not a problem since all u-boot versions I have seen are
not using the cpu_scale_div clock at all (instead they are configuring
the CPU clock to run off cpu_in_sel directly).
The fixes tag points to the latest rework of the CPU clocks. However,
even before the rework it was wrong. Commit 7a29a869434e8b ("clk: meson:
Add support for Meson clock controller") defines MESON_N_WIDTH as 9 (in
drivers/clk/meson/clk-cpu.c). But since the old clk-cpu implementation
this only carries the fixes tag for the CPU clock rewordk.
Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20180927085921.24627-3-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/meson/meson8b.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 580a86d120e8..0da8334f2e43 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -583,7 +583,7 @@ static struct clk_regmap meson8b_cpu_scale_div = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.shift = 20,
- .width = 9,
+ .width = 10,
.table = cpu_scale_table,
.flags = CLK_DIVIDER_ALLOW_ZERO,
},
--
2.19.1
next prev parent reply other threads:[~2019-01-28 17:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20190128155924.51521-1-sashal@kernel.org>
2019-01-28 15:55 ` [PATCH AUTOSEL 4.19 020/258] clk: boston: fix possible memory leak in clk_boston_setup() Sasha Levin
2019-01-28 15:56 ` [PATCH AUTOSEL 4.19 060/258] clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel Sasha Levin
2019-01-28 15:56 ` Sasha Levin [this message]
2019-01-28 15:56 ` [PATCH AUTOSEL 4.19 062/258] clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL Sasha Levin
2019-01-28 15:56 ` [PATCH AUTOSEL 4.19 107/258] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks Sasha Levin
2019-01-28 15:57 ` [PATCH AUTOSEL 4.19 132/258] clk: imx6sl: ensure MMDC CH0 handshake is bypassed Sasha Levin
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