From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FE58C282D8 for ; Fri, 1 Feb 2019 08:30:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D6E621872 for ; Fri, 1 Feb 2019 08:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728701AbfBAIad (ORCPT ); Fri, 1 Feb 2019 03:30:33 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:47459 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727356AbfBAIac (ORCPT ); Fri, 1 Feb 2019 03:30:32 -0500 X-UUID: 51c57c4d8a784351ac2553c61463441d-20190201 X-UUID: 51c57c4d8a784351ac2553c61463441d-20190201 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 374678742; Fri, 01 Feb 2019 16:30:26 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 1 Feb 2019 16:30:24 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 1 Feb 2019 16:30:24 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring CC: James Liao , Fan Chen , , , , , , , Weiyi Lu Subject: [PATCH v4 00/12] Mediatek MT8183 clock and scpsys support Date: Fri, 1 Feb 2019 16:30:03 +0800 Message-ID: <20190201083016.25856-1-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 3302BB800FC02B115B005266083D4613B57A5E5DA2C035EB107724AA37349ADF2000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This series is based on v5.0-rc1 and most of changes are extracted from series below (clock/scpsys common changes for both MT8183 & MT6765) https://patchwork.kernel.org/patch/10528495/ (clock support of MT8183) https://patchwork.kernel.org/patch/10549891/ The whole series is composed of clock common changes for both MT8183 & MT6765 (PATCH 1-3), scpsys common changes for both MT8183 & MT6765 (PATCH 4), clock support of MT8183 (PATCH 5-8), scpsys support of MT8183 (PATCH 9-11) and resend a clock patch long time ago(PTACH 12). change sinve v3: - add fix tag. - small change of mtk_clk_mux data structure. - use of_property_for_each_string to iterate dependent subsys clock of power domain. - document critical clocks. - reduce some clock register error log. - few coding style fix. change sinve v2: - refine for implementation consistency of mtk clk mux. - separate the onoff API into enable/disable API for mtk scpsys. - resend a patch about PLL rate changing. changes since v1: - refine for better code quality. - some minor bug fix of clock part, like incorrect control address and missing clocks.