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From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Chen-Yu Tsai <wens@csie.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	Michael Trimarchi <michael@amarulasolutions.com>,
	linux-amarula@amarulasolutions.com, linux-sunxi@googlegroups.com,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH v7 10/23] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes
Date: Fri,  1 Feb 2019 21:12:19 +0530
Message-ID: <20190201154232.10505-11-jagan@amarulasolutions.com> (raw)
In-Reply-To: <20190201154232.10505-1-jagan@amarulasolutions.com>

TCON dotclock compute the desired DCLK register divider based on panel
pixel clock along with input DCLK or DSI clock dividers from tcon driver.

The current code allowing an input DCLK dividers ranging from 4 to 127,
but the existing dclock logic is unable to compute the desired output
DCLK divider value for new panels instead it ended-up producing unknown
divider values which no longer exists.

So, add the computation logic 'format/lanes' to dclk min and max dividers
and indeed it produced the desired DCLK divider even for the new panels.

This computation logic align with Allwinner A64 BSP, hoping that would work
even for A33.

Tested this on 3 different panels, and below are the desired divider values
with respect to pixel clock frequency.

- 55MHz pixel clock with 4-lane panel, and the desired DSI clock divider
  is 6 with the output parent clock rate of 330MHz.
- 30MHz pixel clock with 4-lane panel, and the desired DSI clock divider
  is 6 with parent clock rate of 180MHz.
- 27.5Mhz pixel clock with 2-lane pane, and the desired DSI clock divider
  is 12 with the output parent clock rate of 330MHz.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 3da75a0c5c5d..4d5a158d9a25 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -342,8 +342,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
 	u32 block_space, start_delay;
 	u32 tcon_div;
 
-	tcon->dclk_min_div = 4;
-	tcon->dclk_max_div = 127;
+	tcon->dclk_min_div = bpp / lanes;
+	tcon->dclk_max_div = bpp / lanes;
 
 	sun4i_tcon0_mode_set_common(tcon, mode);
 
-- 
2.18.0.321.gffc6fa0e3


  parent reply index

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-01 15:42 [PATCH v7 00/23] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2019-02-01 15:42 ` [PATCH v7 01/23] drm/sun4i: sun6i_mipi_dsi: Compute burst mode loop N1 instruction delay Jagan Teki
2019-02-01 15:42 ` [PATCH v7 02/23] drm/sun4i: sun6i_mipi_dsi: Support instruction loop selection Jagan Teki
2019-02-01 15:42 ` [PATCH v7 03/23] drm/sun4i: sun6i_mipi_dsi: Setup burst mode timings Jagan Teki
2019-02-01 15:42 ` [PATCH v7 04/23] drm/sun4i: sun6i_mipi_dsi: Simplify drq to support all modes Jagan Teki
2019-02-01 15:42 ` [PATCH v7 05/23] drm/sun4i: tcon: Export get tcon0 routine Jagan Teki
2019-02-01 15:42 ` [PATCH v7 06/23] drm/sun4i: sun6i_mipi_dsi: Probe tcon0 during dsi_bind Jagan Teki
2019-02-01 15:42 ` [PATCH v7 07/23] drm/sun4i: sun6i_mipi_dsi: Setup burst mode Jagan Teki
2019-02-01 15:42 ` [PATCH v7 08/23] drm/sun4i: sun6i_mipi_dsi: Enable trail_inv and trail_fill controls Jagan Teki
2019-02-01 15:42 ` [PATCH v7 09/23] drm/sun4i: sun6i_mipi_dsi: Enable HBP, HSA_HSE for burst mode Jagan Teki
2019-02-01 15:42 ` Jagan Teki [this message]
2019-02-01 15:42 ` [PATCH v7 11/23] dt-bindings: sun6i-dsi: Add VCC-DSI supply property Jagan Teki
2019-02-01 15:42 ` [PATCH v7 12/23] drm/sun4i: sun6i_mipi_dsi: Add support for VCC-DSI voltage regulator Jagan Teki
2019-02-01 15:42 ` [PATCH v7 13/23] dt-bindings: sun6i-dsi: Add A64 MIPI-DSI compatible Jagan Teki
2019-02-01 15:42 ` [PATCH v7 14/23] dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) Jagan Teki
2019-02-01 15:42 ` [PATCH v7 15/23] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk Jagan Teki
2019-02-01 15:42 ` [PATCH v7 16/23] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
2019-02-01 15:42 ` [PATCH v7 17/23] arm64: dts: allwinner: a64: Add MIPI DSI pipeline Jagan Teki
2019-02-01 15:42 ` [DO NOT MERGE][PATCH v7 18/23] arm64: allwinner: a64: pine64-lts: Enable Feiyang FY07024DI26A30-D DSI panel Jagan Teki
2019-02-01 15:42 ` [PATCH v7 19/23] drm/sun4i: sun6i_mipi_dsi: Add DSI Generic short write 2 param transfer Jagan Teki
2019-02-01 15:42 ` [DO NOT MERGE][PATCH v7 20/23] arm64: dts: allwinner: bananapi-m64: Bananapi S070WV20-CT16 DSI panel Jagan Teki
2019-02-01 15:42 ` [PATCH v7 21/23] drm/sun4i: sun6i_mipi_dsi: Fix DSI hbp timing value Jagan Teki
2019-02-01 15:42 ` [PATCH v7 22/23] drm/sun4i: sun6i_mipi_dsi: Fix DSI hfp " Jagan Teki
2019-02-01 15:42 ` [PATCH v7 23/23] arm64: dts: allwinner: a64-amarula-relic: Add Techstar TS8550B MIPI-DSI panel Jagan Teki
2019-02-01 15:48 ` [PATCH v7 00/23] drm/sun4i: Allwinner A64 MIPI-DSI support Maxime Ripard
2019-02-01 15:51   ` Jagan Teki
2019-02-12  9:46 ` Jagan Teki
2019-02-13  9:03   ` Maxime Ripard
2019-02-13  9:19     ` Jagan Teki
2019-02-14 16:41       ` Jagan Teki

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