* [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
@ 2019-02-02 15:52 Priit Laes
2019-02-05 9:45 ` Maxime Ripard
0 siblings, 1 reply; 9+ messages in thread
From: Priit Laes @ 2019-02-02 15:52 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
linux-arm-kernel, linux-clk, linux-kernel, Jernej Skrabec
Cc: Priit Laes
Recent patch of improving MP clock rate calculations by taking
into account whether adjusting parent rate is allowed, have
unfortunately broken eMMC support on A20 Olinuxino-Lime2-eMMC
boards which fail with following error:
[snip]
EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
EXT4-fs (mmcblk1p4): write access will be enabled during recovery
sunxi-mmc 1c11000.mmc: data error, sending stop command
sunxi-mmc 1c11000.mmc: send stop command failed
[/snip]
Previously, mmc2 clock was requesting 520MHz and settling at 512MHz
clock rate with following parents:
[snip]
pll-ddr-base 2 2 0 768000000 0 0 50000
pll-ddr-other 1 1 0 768000000 0 0 50000
mmc2 0 0 0 51200000 0 0 50000
[/snip]
Now, after the improvements, requested and settled rate are both
520MHz, but as mmc2 clock cannot adjust parent rate, the situation
ends up like this:
[snip]
pll-periph-base 3 3 0 1200000000 0 0 50000
pll-periph 6 6 0 600000000 0 0 50000
mmc2 3 3 0 50000000 0 0 50000
[/snip]
With this patch (allowing mmc2 to set parent rate), we end up with
working tree with both mmc0 (sd-card) and mmc2 (eMMC) working:
[snip]
pll-periph-base 3 3 0 312000000 0 0 50000
mbus 1 1 0 78000000 0 0 50000
pll-periph-sata 1 1 0 26000000 0 0 50000
sata 1 1 0 26000000 0 0 50000
pll-periph 5 5 0 156000000 0 0 50000
mmc2 0 0 0 52000000 0 0 50000
mmc0 0 0 0 39000000 0 0 50000
[/snip]
Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
Signed-off-by: Priit Laes <plaes@plaes.org>
---
drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 129ebd2588fd..605e13b4ef90 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -498,7 +498,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
16, 2, /* P */
24, 2, /* mux */
BIT(31), /* gate */
- 0);
+ CLK_SET_RATE_PARENT);
/* MMC output and sample clocks are not present on A10 */
static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
--
2.11.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-02 15:52 [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock Priit Laes
@ 2019-02-05 9:45 ` Maxime Ripard
2019-02-05 13:44 ` Chen-Yu Tsai
0 siblings, 1 reply; 9+ messages in thread
From: Maxime Ripard @ 2019-02-05 9:45 UTC (permalink / raw)
To: Priit Laes
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
[-- Attachment #1: Type: text/plain, Size: 2138 bytes --]
On Sat, Feb 02, 2019 at 05:52:09PM +0200, Priit Laes wrote:
> Recent patch of improving MP clock rate calculations by taking
> into account whether adjusting parent rate is allowed, have
> unfortunately broken eMMC support on A20 Olinuxino-Lime2-eMMC
> boards which fail with following error:
>
> [snip]
> EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> sunxi-mmc 1c11000.mmc: data error, sending stop command
> sunxi-mmc 1c11000.mmc: send stop command failed
> [/snip]
>
> Previously, mmc2 clock was requesting 520MHz and settling at 512MHz
> clock rate with following parents:
> [snip]
> pll-ddr-base 2 2 0 768000000 0 0 50000
> pll-ddr-other 1 1 0 768000000 0 0 50000
> mmc2 0 0 0 51200000 0 0 50000
> [/snip]
>
> Now, after the improvements, requested and settled rate are both
> 520MHz, but as mmc2 clock cannot adjust parent rate, the situation
> ends up like this:
> [snip]
> pll-periph-base 3 3 0 1200000000 0 0 50000
> pll-periph 6 6 0 600000000 0 0 50000
> mmc2 3 3 0 50000000 0 0 50000
> [/snip]
>
> With this patch (allowing mmc2 to set parent rate), we end up with
> working tree with both mmc0 (sd-card) and mmc2 (eMMC) working:
> [snip]
> pll-periph-base 3 3 0 312000000 0 0 50000
> mbus 1 1 0 78000000 0 0 50000
> pll-periph-sata 1 1 0 26000000 0 0 50000
> sata 1 1 0 26000000 0 0 50000
> pll-periph 5 5 0 156000000 0 0 50000
> mmc2 0 0 0 52000000 0 0 50000
> mmc0 0 0 0 39000000 0 0 50000
> [/snip]
>
> Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
> Signed-off-by: Priit Laes <plaes@plaes.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-05 9:45 ` Maxime Ripard
@ 2019-02-05 13:44 ` Chen-Yu Tsai
2019-02-06 9:20 ` Maxime Ripard
0 siblings, 1 reply; 9+ messages in thread
From: Chen-Yu Tsai @ 2019-02-05 13:44 UTC (permalink / raw)
To: Maxime Ripard
Cc: Priit Laes, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
On Tue, Feb 5, 2019 at 5:45 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Sat, Feb 02, 2019 at 05:52:09PM +0200, Priit Laes wrote:
> > Recent patch of improving MP clock rate calculations by taking
> > into account whether adjusting parent rate is allowed, have
> > unfortunately broken eMMC support on A20 Olinuxino-Lime2-eMMC
> > boards which fail with following error:
> >
> > [snip]
> > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > sunxi-mmc 1c11000.mmc: send stop command failed
> > [/snip]
> >
> > Previously, mmc2 clock was requesting 520MHz and settling at 512MHz
> > clock rate with following parents:
You mean 52 and 51.2 MHz.
> > [snip]
> > pll-ddr-base 2 2 0 768000000 0 0 50000
> > pll-ddr-other 1 1 0 768000000 0 0 50000
> > mmc2 0 0 0 51200000 0 0 50000
> > [/snip]
> >
> > Now, after the improvements, requested and settled rate are both
> > 520MHz, but as mmc2 clock cannot adjust parent rate, the situation
> > ends up like this:
> > [snip]
> > pll-periph-base 3 3 0 1200000000 0 0 50000
> > pll-periph 6 6 0 600000000 0 0 50000
> > mmc2 3 3 0 50000000 0 0 50000
> > [/snip]
> >
> > With this patch (allowing mmc2 to set parent rate), we end up with
> > working tree with both mmc0 (sd-card) and mmc2 (eMMC) working:
> > [snip]
> > pll-periph-base 3 3 0 312000000 0 0 50000
> > mbus 1 1 0 78000000 0 0 50000
> > pll-periph-sata 1 1 0 26000000 0 0 50000
> > sata 1 1 0 26000000 0 0 50000
> > pll-periph 5 5 0 156000000 0 0 50000
> > mmc2 0 0 0 52000000 0 0 50000
> > mmc0 0 0 0 39000000 0 0 50000
> > [/snip]
> >
> > Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
> > Signed-off-by: Priit Laes <plaes@plaes.org>
>
> Applied, thanks!
> Maxime
I'm concerned for other users of the PLL-PERIPH clock. AFAIK
all of them, except the HRTIMER, expect the clock rate to stay
the same and not change underneath them. And SATA expects it to
be at 600 MHz, as the datasheet says. And while it may not directly
apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
reduced rate of 50 MHz just fine.
In the commit in question, clocks without CLK_SET_RATE_PARENT
should be using the old code (now in the if conditional block),
i.e. the behavior should not have changed.
I don't think this actually "fixes" whatever bug was introduced,
but only papers over the issue, and possible introduces further
issues for other users.
Regards
ChenYu
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-05 13:44 ` Chen-Yu Tsai
@ 2019-02-06 9:20 ` Maxime Ripard
2019-02-06 10:03 ` Priit Laes
0 siblings, 1 reply; 9+ messages in thread
From: Maxime Ripard @ 2019-02-06 9:20 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Priit Laes, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
[-- Attachment #1: Type: text/plain, Size: 3344 bytes --]
On Tue, Feb 05, 2019 at 09:44:02PM +0800, Chen-Yu Tsai wrote:
> On Tue, Feb 5, 2019 at 5:45 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Sat, Feb 02, 2019 at 05:52:09PM +0200, Priit Laes wrote:
> > > Recent patch of improving MP clock rate calculations by taking
> > > into account whether adjusting parent rate is allowed, have
> > > unfortunately broken eMMC support on A20 Olinuxino-Lime2-eMMC
> > > boards which fail with following error:
> > >
> > > [snip]
> > > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > > sunxi-mmc 1c11000.mmc: send stop command failed
> > > [/snip]
> > >
> > > Previously, mmc2 clock was requesting 520MHz and settling at 512MHz
> > > clock rate with following parents:
>
> You mean 52 and 51.2 MHz.
>
> > > [snip]
> > > pll-ddr-base 2 2 0 768000000 0 0 50000
> > > pll-ddr-other 1 1 0 768000000 0 0 50000
> > > mmc2 0 0 0 51200000 0 0 50000
> > > [/snip]
> > >
> > > Now, after the improvements, requested and settled rate are both
> > > 520MHz, but as mmc2 clock cannot adjust parent rate, the situation
> > > ends up like this:
> > > [snip]
> > > pll-periph-base 3 3 0 1200000000 0 0 50000
> > > pll-periph 6 6 0 600000000 0 0 50000
> > > mmc2 3 3 0 50000000 0 0 50000
> > > [/snip]
> > >
> > > With this patch (allowing mmc2 to set parent rate), we end up with
> > > working tree with both mmc0 (sd-card) and mmc2 (eMMC) working:
> > > [snip]
> > > pll-periph-base 3 3 0 312000000 0 0 50000
> > > mbus 1 1 0 78000000 0 0 50000
> > > pll-periph-sata 1 1 0 26000000 0 0 50000
> > > sata 1 1 0 26000000 0 0 50000
> > > pll-periph 5 5 0 156000000 0 0 50000
> > > mmc2 0 0 0 52000000 0 0 50000
> > > mmc0 0 0 0 39000000 0 0 50000
> > > [/snip]
> > >
> > > Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
> > > Signed-off-by: Priit Laes <plaes@plaes.org>
> >
> > Applied, thanks!
> > Maxime
>
> I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> all of them, except the HRTIMER, expect the clock rate to stay
> the same and not change underneath them. And SATA expects it to
> be at 600 MHz, as the datasheet says. And while it may not directly
> apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> reduced rate of 50 MHz just fine.
>
> In the commit in question, clocks without CLK_SET_RATE_PARENT
> should be using the old code (now in the if conditional block),
> i.e. the behavior should not have changed.
>
> I don't think this actually "fixes" whatever bug was introduced,
> but only papers over the issue, and possible introduces further
> issues for other users.
You're right, I've overlooked that it was pll-periph being
affected. I've dropped it for now.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-06 9:20 ` Maxime Ripard
@ 2019-02-06 10:03 ` Priit Laes
2019-02-06 15:52 ` Maxime Ripard
0 siblings, 1 reply; 9+ messages in thread
From: Priit Laes @ 2019-02-06 10:03 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
On Wed, Feb 06, 2019 at 10:20:00AM +0100, Maxime Ripard wrote:
> On Tue, Feb 05, 2019 at 09:44:02PM +0800, Chen-Yu Tsai wrote:
> > On Tue, Feb 5, 2019 at 5:45 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > On Sat, Feb 02, 2019 at 05:52:09PM +0200, Priit Laes wrote:
> > > > Recent patch of improving MP clock rate calculations by taking
> > > > into account whether adjusting parent rate is allowed, have
> > > > unfortunately broken eMMC support on A20 Olinuxino-Lime2-eMMC
> > > > boards which fail with following error:
> > > >
> > > > [snip]
> > > > EXT4-fs (mmcblk1p4): INFO: recovery required on readonly filesystem
> > > > EXT4-fs (mmcblk1p4): write access will be enabled during recovery
> > > > sunxi-mmc 1c11000.mmc: data error, sending stop command
> > > > sunxi-mmc 1c11000.mmc: send stop command failed
> > > > [/snip]
> > > >
> > > > Previously, mmc2 clock was requesting 520MHz and settling at 512MHz
> > > > clock rate with following parents:
> >
> > You mean 52 and 51.2 MHz.
> >
> > > > [snip]
> > > > pll-ddr-base 2 2 0 768000000 0 0 50000
> > > > pll-ddr-other 1 1 0 768000000 0 0 50000
> > > > mmc2 0 0 0 51200000 0 0 50000
> > > > [/snip]
> > > >
> > > > Now, after the improvements, requested and settled rate are both
> > > > 520MHz, but as mmc2 clock cannot adjust parent rate, the situation
> > > > ends up like this:
> > > > [snip]
> > > > pll-periph-base 3 3 0 1200000000 0 0 50000
> > > > pll-periph 6 6 0 600000000 0 0 50000
> > > > mmc2 3 3 0 50000000 0 0 50000
> > > > [/snip]
> > > >
> > > > With this patch (allowing mmc2 to set parent rate), we end up with
> > > > working tree with both mmc0 (sd-card) and mmc2 (eMMC) working:
> > > > [snip]
> > > > pll-periph-base 3 3 0 312000000 0 0 50000
> > > > mbus 1 1 0 78000000 0 0 50000
> > > > pll-periph-sata 1 1 0 26000000 0 0 50000
> > > > sata 1 1 0 26000000 0 0 50000
> > > > pll-periph 5 5 0 156000000 0 0 50000
> > > > mmc2 0 0 0 52000000 0 0 50000
> > > > mmc0 0 0 0 39000000 0 0 50000
> > > > [/snip]
> > > >
> > > > Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
> > > > Signed-off-by: Priit Laes <plaes@plaes.org>
> > >
> > > Applied, thanks!
> > > Maxime
> >
> > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > all of them, except the HRTIMER, expect the clock rate to stay
> > the same and not change underneath them. And SATA expects it to
> > be at 600 MHz, as the datasheet says. And while it may not directly
> > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > reduced rate of 50 MHz just fine.
> >
> > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > should be using the old code (now in the if conditional block),
> > i.e. the behavior should not have changed.
> >
> > I don't think this actually "fixes" whatever bug was introduced,
> > but only papers over the issue, and possible introduces further
> > issues for other users.
>
> You're right, I've overlooked that it was pll-periph being
> affected. I've dropped it for now.
Any ideas what could be done. I currently have no time to debug it, but it affects existing systems.
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-06 10:03 ` Priit Laes
@ 2019-02-06 15:52 ` Maxime Ripard
2019-02-11 14:35 ` Priit Laes
0 siblings, 1 reply; 9+ messages in thread
From: Maxime Ripard @ 2019-02-06 15:52 UTC (permalink / raw)
To: Priit Laes
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
[-- Attachment #1: Type: text/plain, Size: 1335 bytes --]
Hi,
On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > all of them, except the HRTIMER, expect the clock rate to stay
> > > the same and not change underneath them. And SATA expects it to
> > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > reduced rate of 50 MHz just fine.
> > >
> > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > should be using the old code (now in the if conditional block),
> > > i.e. the behavior should not have changed.
> > >
> > > I don't think this actually "fixes" whatever bug was introduced,
> > > but only papers over the issue, and possible introduces further
> > > issues for other users.
> >
> > You're right, I've overlooked that it was pll-periph being
> > affected. I've dropped it for now.
>
> Any ideas what could be done. I currently have no time to debug it,
> but it affects existing systems.
I can't find what would change with that commit either if the flag
isn't set, so looking at the register state before and after that
commit would help I guess?
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-06 15:52 ` Maxime Ripard
@ 2019-02-11 14:35 ` Priit Laes
2019-02-11 15:34 ` Maxime Ripard
0 siblings, 1 reply; 9+ messages in thread
From: Priit Laes @ 2019-02-11 14:35 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
On Wed, Feb 06, 2019 at 04:52:27PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > > all of them, except the HRTIMER, expect the clock rate to stay
> > > > the same and not change underneath them. And SATA expects it to
> > > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > > reduced rate of 50 MHz just fine.
> > > >
> > > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > > should be using the old code (now in the if conditional block),
> > > > i.e. the behavior should not have changed.
> > > >
> > > > I don't think this actually "fixes" whatever bug was introduced,
> > > > but only papers over the issue, and possible introduces further
> > > > issues for other users.
> > >
> > > You're right, I've overlooked that it was pll-periph being
> > > affected. I've dropped it for now.
> >
> > Any ideas what could be done. I currently have no time to debug it,
> > but it affects existing systems.
>
> I can't find what would change with that commit either if the flag
> isn't set, so looking at the register state before and after that
> commit would help I guess?
Register dump without the patch:
$ busybox devmem 0x01c20090
0x0250030E
pll-ddr-base 2 2 0 768000000 0 0 50000
pll-ddr-other 1 1 0 768000000 0 0 50000
mmc2 3 3 0 51200000 0 0 50000
Register dump with patch applied, booted from mmc0 and after mounting emmc:
$ busybox devmem 0x01c20090
0x8140020B
pll-periph-base 3 3 0 1200000000 0 0 50000
pll-periph 6 6 0 600000000 0 0 50000
mmc2 3 3 0 50000000 0 0 50000
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-11 14:35 ` Priit Laes
@ 2019-02-11 15:34 ` Maxime Ripard
2019-02-12 9:45 ` Priit Laes
0 siblings, 1 reply; 9+ messages in thread
From: Maxime Ripard @ 2019-02-11 15:34 UTC (permalink / raw)
To: Priit Laes
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]
On Mon, Feb 11, 2019 at 02:35:52PM +0000, Priit Laes wrote:
> On Wed, Feb 06, 2019 at 04:52:27PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > > > all of them, except the HRTIMER, expect the clock rate to stay
> > > > > the same and not change underneath them. And SATA expects it to
> > > > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > > > reduced rate of 50 MHz just fine.
> > > > >
> > > > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > > > should be using the old code (now in the if conditional block),
> > > > > i.e. the behavior should not have changed.
> > > > >
> > > > > I don't think this actually "fixes" whatever bug was introduced,
> > > > > but only papers over the issue, and possible introduces further
> > > > > issues for other users.
> > > >
> > > > You're right, I've overlooked that it was pll-periph being
> > > > affected. I've dropped it for now.
> > >
> > > Any ideas what could be done. I currently have no time to debug it,
> > > but it affects existing systems.
> >
> > I can't find what would change with that commit either if the flag
> > isn't set, so looking at the register state before and after that
> > commit would help I guess?
>
> Register dump without the patch:
>
> $ busybox devmem 0x01c20090
> 0x0250030E
>
> pll-ddr-base 2 2 0 768000000 0 0 50000
> pll-ddr-other 1 1 0 768000000 0 0 50000
> mmc2 3 3 0 51200000 0 0 50000
>
> Register dump with patch applied, booted from mmc0 and after mounting emmc:
>
> $ busybox devmem 0x01c20090
> 0x8140020B
>
> pll-periph-base 3 3 0 1200000000 0 0 50000
> pll-periph 6 6 0 600000000 0 0 50000
> mmc2 3 3 0 50000000 0 0 50000
I meant the whole Clock controller, ideally a diff between the two
states would be great.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
2019-02-11 15:34 ` Maxime Ripard
@ 2019-02-12 9:45 ` Priit Laes
0 siblings, 0 replies; 9+ messages in thread
From: Priit Laes @ 2019-02-12 9:45 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Michael Turquette, Stephen Boyd, linux-arm-kernel,
linux-clk, linux-kernel, Jernej Skrabec
On Mon, Feb 11, 2019 at 04:34:02PM +0100, Maxime Ripard wrote:
> On Mon, Feb 11, 2019 at 02:35:52PM +0000, Priit Laes wrote:
> > On Wed, Feb 06, 2019 at 04:52:27PM +0100, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > > > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > > > > all of them, except the HRTIMER, expect the clock rate to stay
> > > > > > the same and not change underneath them. And SATA expects it to
> > > > > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > > > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > > > > reduced rate of 50 MHz just fine.
> > > > > >
> > > > > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > > > > should be using the old code (now in the if conditional block),
> > > > > > i.e. the behavior should not have changed.
> > > > > >
> > > > > > I don't think this actually "fixes" whatever bug was introduced,
> > > > > > but only papers over the issue, and possible introduces further
> > > > > > issues for other users.
> > > > >
> > > > > You're right, I've overlooked that it was pll-periph being
> > > > > affected. I've dropped it for now.
> > > >
> > > > Any ideas what could be done. I currently have no time to debug it,
> > > > but it affects existing systems.
> > >
> > > I can't find what would change with that commit either if the flag
> > > isn't set, so looking at the register state before and after that
> > > commit would help I guess?
> >
> > Register dump without the patch:
> >
> > $ busybox devmem 0x01c20090
> > 0x0250030E
> >
> > pll-ddr-base 2 2 0 768000000 0 0 50000
> > pll-ddr-other 1 1 0 768000000 0 0 50000
> > mmc2 3 3 0 51200000 0 0 50000
> >
> > Register dump with patch applied, booted from mmc0 and after mounting emmc:
> >
> > $ busybox devmem 0x01c20090
> > 0x8140020B
> >
> > pll-periph-base 3 3 0 1200000000 0 0 50000
> > pll-periph 6 6 0 600000000 0 0 50000
> > mmc2 3 3 0 50000000 0 0 50000
>
> I meant the whole Clock controller, ideally a diff between the two
> states would be great.
I have uploaded the raw files here:
https://gist.github.com/plaes/3465386d8aa55fa70fd3997310719828
The test scenario is following:
1) Boot via FEL (u-boot + zImage + boot.scr) and load root fs from
sd-card / mmc0
2) ssh into machine and dump register space
- no-patch-before-mount.dump
- no-patch-post-mount.dump
3) Attempt to mount emmc / mmc2 and dump ccu register space
- with-patch-before-mount.dump
- with-patch-post-mount.dump
Firstly, I noticed that first 0x200 bits are mirrored:
0x1c20000 = 0x1c20200
0x1c20004 = 0x1c20204
...
01xc201fc = 0x1c203fc
And here come the diffs:
a) Diff before mount vs patch / reverted patch:
mmc2:
-0x1c20090: 0x0250030E
+0x1c20090: 0x0140020B
unk1: (mirrored ahb?, this one's flaky due to mmc runtime suspend)
-0x1c20260: 0x1200C17F
+0x1c20260: 0x1200C07F
unk2: (mirrored mmc2?)
-0x1c20290: 0x0250030E
+0x1c20290: 0x0140020B
b) Diff post-mount vs patch / reverted patch:
ahb (this one's flaky, possibly due to runtime suspend for mmc):
-0x1c20060: 0x1200C07F or 0x1200C17F
+0x1c20060: 0x1200C47F
mmc2:
-0x1c20090: 0x0250030E
+0x1c20090: 0x8140020B
unk1:
-0x1c20260: 0x1200C07F
+0x1c20260: 0x1200C47F
unk3:
-0x1c20288: 0x8140030B
+0x1c20288: 0x0140030B
unk2: (mirrored mmc2?)
-0x1c20290: 0x0250030E
+0x1c20290: 0x8140020B
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-02-12 9:45 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-02 15:52 [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock Priit Laes
2019-02-05 9:45 ` Maxime Ripard
2019-02-05 13:44 ` Chen-Yu Tsai
2019-02-06 9:20 ` Maxime Ripard
2019-02-06 10:03 ` Priit Laes
2019-02-06 15:52 ` Maxime Ripard
2019-02-11 14:35 ` Priit Laes
2019-02-11 15:34 ` Maxime Ripard
2019-02-12 9:45 ` Priit Laes
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