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* [PATCH v1 1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72
@ 2019-02-11  7:15 Seiya Wang
  2019-02-11  7:15 ` [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC Seiya Wang
  0 siblings, 1 reply; 3+ messages in thread
From: Seiya Wang @ 2019-02-11  7:15 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, Matthias Brugger, Michael Turquette,
	Stephen Boyd
  Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
	linux-clk, Seiya Wang

The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57.

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 44374c506a1c..99675c51577a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -178,12 +178,12 @@
 
 		cpu2: cpu@100 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a57";
+			compatible = "arm,cortex-a72";
 			reg = <0x100>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			#cooling-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_CA57SEL>,
+			clocks = <&infracfg CLK_INFRA_CA72SEL>,
 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster1_opp>;
@@ -191,12 +191,12 @@
 
 		cpu3: cpu@101 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a57";
+			compatible = "arm,cortex-a72";
 			reg = <0x101>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			#cooling-cells = <2>;
-			clocks = <&infracfg CLK_INFRA_CA57SEL>,
+			clocks = <&infracfg CLK_INFRA_CA72SEL>,
 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
 			clock-names = "cpu", "intermediate";
 			operating-points-v2 = <&cluster1_opp>;
-- 
2.14.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC
  2019-02-11  7:15 [PATCH v1 1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 Seiya Wang
@ 2019-02-11  7:15 ` Seiya Wang
  2019-02-11  9:04   ` Matthias Brugger
  0 siblings, 1 reply; 3+ messages in thread
From: Seiya Wang @ 2019-02-11  7:15 UTC (permalink / raw)
  To: Rob Herring, Mark Rutland, Matthias Brugger, Michael Turquette,
	Stephen Boyd
  Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
	linux-clk, Seiya Wang

Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.

Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c      | 4 ++--
 include/dt-bindings/clock/mt8173-clk.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 96c292c3e440..deedeb3ea33b 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = {
 	"univpll"
 };
 
-static const char * const ca57_parents[] __initconst = {
+static const char * const ca72_parents[] __initconst = {
 	"clk26m",
 	"armca15pll",
 	"mainpll",
@@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = {
 
 static const struct mtk_composite cpu_muxes[] __initconst = {
 	MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
-	MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
+	MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
 };
 
 static const struct mtk_composite top_muxes[] __initconst = {
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 8aea623dd518..f7e5356fd602 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -194,7 +194,7 @@
 #define CLK_INFRA_PMICWRAP		11
 #define CLK_INFRA_CLK_13M		12
 #define CLK_INFRA_CA53SEL               13
-#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_CA72SEL               14
 #define CLK_INFRA_NR_CLK                15
 
 /* PERI_SYS */
-- 
2.14.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC
  2019-02-11  7:15 ` [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC Seiya Wang
@ 2019-02-11  9:04   ` Matthias Brugger
  0 siblings, 0 replies; 3+ messages in thread
From: Matthias Brugger @ 2019-02-11  9:04 UTC (permalink / raw)
  To: Seiya Wang, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd
  Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, linux-clk



On 11/02/2019 08:15, Seiya Wang wrote:
> Change cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.
> 
> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>  drivers/clk/mediatek/clk-mt8173.c      | 4 ++--
>  include/dt-bindings/clock/mt8173-clk.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 96c292c3e440..deedeb3ea33b 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -533,7 +533,7 @@ static const char * const ca53_parents[] __initconst = {
>  	"univpll"
>  };
>  
> -static const char * const ca57_parents[] __initconst = {
> +static const char * const ca72_parents[] __initconst = {
>  	"clk26m",
>  	"armca15pll",
>  	"mainpll",
> @@ -542,7 +542,7 @@ static const char * const ca57_parents[] __initconst = {
>  
>  static const struct mtk_composite cpu_muxes[] __initconst = {
>  	MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
> -	MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
> +	MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
>  };
>  
>  static const struct mtk_composite top_muxes[] __initconst = {
> diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
> index 8aea623dd518..f7e5356fd602 100644
> --- a/include/dt-bindings/clock/mt8173-clk.h
> +++ b/include/dt-bindings/clock/mt8173-clk.h
> @@ -194,7 +194,7 @@
>  #define CLK_INFRA_PMICWRAP		11
>  #define CLK_INFRA_CLK_13M		12
>  #define CLK_INFRA_CA53SEL               13
> -#define CLK_INFRA_CA57SEL               14
> +#define CLK_INFRA_CA72SEL               14
>  #define CLK_INFRA_NR_CLK                15
>  
>  /* PERI_SYS */
> 

^ permalink raw reply	[flat|nested] 3+ messages in thread

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Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-02-11  7:15 [PATCH v1 1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 Seiya Wang
2019-02-11  7:15 ` [PATCH v1 2/2] clk: mediatek: correct cpu clock name for MT8173 SoC Seiya Wang
2019-02-11  9:04   ` Matthias Brugger

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