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* [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h
@ 2019-02-11  7:39 Vinod Koul
  2019-02-11  7:39 ` [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Vinod Koul @ 2019-02-11  7:39 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	David Brown, linux-soc, linux-clk

Remove the redundant empty lines crept in.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Changes in v2:
	Add new patch to remove empty line

 drivers/clk/qcom/clk-rcg.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e5eca8a1abe4..91336a030179 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -71,7 +71,6 @@ struct src_sel {
  * @freq_tbl: frequency table
  * @clkr: regmap clock handle
  * @lock: register lock
- *
  */
 struct clk_rcg {
 	u32		ns_reg;
@@ -107,7 +106,6 @@ extern const struct clk_ops clk_rcg_lcc_ops;
  * @freq_tbl: frequency table
  * @clkr: regmap clock handle
  * @lock: register lock
- *
  */
 struct clk_dyn_rcg {
 	u32	ns_reg[2];
@@ -140,7 +138,6 @@ extern const struct clk_ops clk_dyn_rcg_ops;
  * @parent_map: map from software's parent index to hardware's src_sel field
  * @freq_tbl: frequency table
  * @clkr: regmap clock handle
- *
  */
 struct clk_rcg2 {
 	u32			cmd_rcgr;
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
  2019-02-11  7:39 [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Vinod Koul
@ 2019-02-11  7:39 ` Vinod Koul
  2019-02-21 22:18   ` Stephen Boyd
  2019-02-11  7:39 ` [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Vinod Koul
  2019-02-21 22:18 ` [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Stephen Boyd
  2 siblings, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2019-02-11  7:39 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd
  Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Andy Gross,
	David Brown, linux-soc, linux-clk, Anu Ramanathan, Shawn Guo,
	Vinod Koul

From: Taniya Das <tdas@codeaurora.org>

The RCG CFG/M/N/D register base could be at a different offset than
the CMD register, so introduce a cfg_offset to identify the offset
with respect to the CMD RCGR register.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Changes in v2:
 - add macros and update comment

 drivers/clk/qcom/clk-rcg.h  |  2 ++
 drivers/clk/qcom/clk-rcg2.c | 24 ++++++++++++++----------
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 91336a030179..c25b57c3cbc8 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -138,6 +138,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
  * @parent_map: map from software's parent index to hardware's src_sel field
  * @freq_tbl: frequency table
  * @clkr: regmap clock handle
+ * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
  */
 struct clk_rcg2 {
 	u32			cmd_rcgr;
@@ -147,6 +148,7 @@ struct clk_rcg2 {
 	const struct parent_map	*parent_map;
 	const struct freq_tbl	*freq_tbl;
 	struct clk_regmap	clkr;
+	u8			cfg_off;
 };
 
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 6e3bd195d012..8c02bffe50df 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -41,6 +41,11 @@
 #define N_REG			0xc
 #define D_REG			0x10
 
+#define RCG_CFG_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
+#define RCG_M_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
+#define RCG_N_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
+#define RCG_D_OFFSET(rcg)	((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
+
 /* Dynamic Frequency Scaling */
 #define MAX_PERF_LEVEL		8
 #define SE_CMD_DFSR_OFFSET	0x14
@@ -74,7 +79,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
 	u32 cfg;
 	int i, ret;
 
-	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
+	ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
 	if (ret)
 		goto err;
 
@@ -123,7 +128,7 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
 	int ret;
 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 
-	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+	ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
 				 CFG_SRC_SEL_MASK, cfg);
 	if (ret)
 		return ret;
@@ -162,13 +167,13 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 	u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
 
-	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
+	regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
 
 	if (rcg->mnd_width) {
 		mask = BIT(rcg->mnd_width) - 1;
-		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
+		regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
 		m &= mask;
-		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
+		regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
 		n =  ~n;
 		n &= mask;
 		n += m;
@@ -263,17 +268,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	if (rcg->mnd_width && f->n) {
 		mask = BIT(rcg->mnd_width) - 1;
 		ret = regmap_update_bits(rcg->clkr.regmap,
-				rcg->cmd_rcgr + M_REG, mask, f->m);
+				RCG_M_OFFSET(rcg), mask, f->m);
 		if (ret)
 			return ret;
 
 		ret = regmap_update_bits(rcg->clkr.regmap,
-				rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
+				RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
 		if (ret)
 			return ret;
 
 		ret = regmap_update_bits(rcg->clkr.regmap,
-				rcg->cmd_rcgr + D_REG, mask, ~f->n);
+				RCG_D_OFFSET(rcg), mask, ~f->n);
 		if (ret)
 			return ret;
 	}
@@ -284,8 +289,7 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
 	if (rcg->mnd_width && f->n && (f->m != f->n))
 		cfg |= CFG_MODE_DUAL_EDGE;
-
-	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
+	return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
 					mask, cfg);
 }
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
  2019-02-11  7:39 [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Vinod Koul
  2019-02-11  7:39 ` [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
@ 2019-02-11  7:39 ` Vinod Koul
  2019-02-21 22:18   ` Stephen Boyd
  2019-02-21 22:18 ` [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Stephen Boyd
  2 siblings, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2019-02-11  7:39 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd
  Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Andy Gross,
	David Brown, linux-soc, linux-clk, Anu Ramanathan, Shawn Guo,
	Vinod Koul

From: Taniya Das <tdas@codeaurora.org>

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Changes in v2:
	Update changelog to indicate that uart3 alone suffers from this

 drivers/clk/qcom/gcc-qcs404.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a7b2fe0fe505..5a62f64ada93 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.cmd_rcgr = 0x4014,
 	.mnd_width = 16,
 	.hid_width = 5,
+	.cfg_off = 0x20,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
-- 
2.20.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h
  2019-02-11  7:39 [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Vinod Koul
  2019-02-11  7:39 ` [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
  2019-02-11  7:39 ` [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Vinod Koul
@ 2019-02-21 22:18 ` Stephen Boyd
  2 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-21 22:18 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Vinod Koul
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	David Brown, linux-soc, linux-clk

Quoting Vinod Koul (2019-02-10 23:39:26)
> Remove the redundant empty lines crept in.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs
  2019-02-11  7:39 ` [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
@ 2019-02-21 22:18   ` Stephen Boyd
  0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-21 22:18 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Vinod Koul
  Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Andy Gross,
	David Brown, linux-soc, linux-clk, Anu Ramanathan, Shawn Guo,
	Vinod Koul

Quoting Vinod Koul (2019-02-10 23:39:27)
> From: Taniya Das <tdas@codeaurora.org>
> 
> The RCG CFG/M/N/D register base could be at a different offset than
> the CMD register, so introduce a cfg_offset to identify the offset
> with respect to the CMD RCGR register.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock
  2019-02-11  7:39 ` [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Vinod Koul
@ 2019-02-21 22:18   ` Stephen Boyd
  0 siblings, 0 replies; 6+ messages in thread
From: Stephen Boyd @ 2019-02-21 22:18 UTC (permalink / raw)
  To: Michael Turquette, Stephen Boyd, Vinod Koul
  Cc: linux-arm-msm, Bjorn Andersson, Taniya Das, Andy Gross,
	David Brown, linux-soc, linux-clk, Anu Ramanathan, Shawn Guo,
	Vinod Koul

Quoting Vinod Koul (2019-02-10 23:39:28)
> From: Taniya Das <tdas@codeaurora.org>
> 
> The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
> only for blsp1_uart3 clock, so add it for uart3 only.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 6+ messages in thread

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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-11  7:39 [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Vinod Koul
2019-02-11  7:39 ` [PATCH v2 2/3] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Vinod Koul
2019-02-21 22:18   ` Stephen Boyd
2019-02-11  7:39 ` [PATCH v2 3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Vinod Koul
2019-02-21 22:18   ` Stephen Boyd
2019-02-21 22:18 ` [PATCH v2 1/3] clk: qcom: remove empty lines in clk-rcg.h Stephen Boyd

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