From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: kernel@pengutronix.de,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
Jolly Shah <jolly.shah@xilinx.com>,
Michael Tretter <m.tretter@pengutronix.de>
Subject: [PATCH v2 3/4] clk: zynqmp: fix check for fractional clock
Date: Tue, 19 Mar 2019 11:01:46 +0100 [thread overview]
Message-ID: <20190319100147.4178-4-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20190319100147.4178-1-m.tretter@pengutronix.de>
The firmware sets BIT(13) in clkflag to mark a divider as fractional
divider. The clock driver copies the clkflag straight to the flags of
the common clock framework. In the common clk framework flags, BIT(13)
is defined as CLK_DUTY_CYCLE_PARENT.
Add a new field to the zynqmp_clk_divider to specify if a divider is a
fractional devider. Set this field based on the clkflag when registering
a divider.
At the same time, unset BIT(13) from clkflag when copying the flags to
the common clk framework flags.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
v1 -> v2:
- add is_frac field to zynqmp_clk_divider
- remove CLK_FRAC from flags when copying to common clock framework
---
drivers/clk/zynqmp/divider.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 16a1f021b4f2..7ee54c3fe20f 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -31,12 +31,14 @@
* struct zynqmp_clk_divider - adjustable divider clock
* @hw: handle between common and hardware-specific interfaces
* @flags: Hardware specific flags
+ * @is_frac: The divider is a fractional divider
* @clk_id: Id of clock
* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
*/
struct zynqmp_clk_divider {
struct clk_hw hw;
u8 flags;
+ bool is_frac;
u32 clk_id;
u32 div_type;
};
@@ -116,8 +118,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
bestdiv = zynqmp_divider_get_val(*prate, rate);
- if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
- (divider->flags & CLK_FRAC))
+ if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
bestdiv = rate % *prate ? 1 : bestdiv;
*prate = rate * bestdiv;
@@ -195,11 +196,13 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
init.name = name;
init.ops = &zynqmp_clk_divider_ops;
- init.flags = nodes->flag;
+ /* CLK_FRAC is not defined in the common clk framework */
+ init.flags = nodes->flag & ~CLK_FRAC;
init.parent_names = parents;
init.num_parents = 1;
/* struct clk_divider assignments */
+ div->is_frac = !!(nodes->flag & CLK_FRAC);
div->flags = nodes->type_flag;
div->hw.init = &init;
div->clk_id = clk_id;
--
2.20.1
next prev parent reply other threads:[~2019-03-19 10:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 10:01 [PATCH v2 0/4] clk: zynqmp: fix CLK_FRAC and various cleanups Michael Tretter
2019-03-19 10:01 ` [PATCH v2 1/4] clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents Michael Tretter
2019-04-11 18:41 ` Stephen Boyd
2019-03-19 10:01 ` [PATCH v2 2/4] clk: zynqmp: do not export zynqmp_clk_register_* functions Michael Tretter
2019-04-11 18:41 ` Stephen Boyd
2019-03-19 10:01 ` Michael Tretter [this message]
2019-04-11 18:41 ` [PATCH v2 3/4] clk: zynqmp: fix check for fractional clock Stephen Boyd
2019-03-19 10:01 ` [PATCH v2 4/4] clk: zynqmp: use structs for clk query responses Michael Tretter
2019-04-04 8:16 ` [PATCH v2 0/4] clk: zynqmp: fix CLK_FRAC and various cleanups Michael Tretter
2019-04-11 18:40 ` Stephen Boyd
2019-04-12 9:36 ` Michael Tretter
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