From: Rob Herring <robh@kernel.org>
To: Mike Looijmans <mike.looijmans@topic.nl>
Cc: devicetree@vger.kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, mark.rutland@arm.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: Add silabs,si5341
Date: Wed, 1 May 2019 19:17:21 -0500 [thread overview]
Message-ID: <20190502001721.GA29391@bogus> (raw)
In-Reply-To: <20190424090216.18417-1-mike.looijmans@topic.nl>
On Wed, Apr 24, 2019 at 11:02:16AM +0200, Mike Looijmans wrote:
> Adds the devicetree bindings for the si5341 driver that supports the
Bindings are for h/w, not a driver.
Perhaps 'dt-bindings: clock: ...' to give a bit more clue what this is
in the subject.
> Si5341 and Si5340 chips.
>
> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
> ---
> .../bindings/clock/silabs,si5341.txt | 141 ++++++++++++++++++
> 1 file changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5341.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.txt b/Documentation/devicetree/bindings/clock/silabs,si5341.txt
> new file mode 100644
> index 000000000000..1a00dd83100f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.txt
> @@ -0,0 +1,141 @@
> +Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator.
> +
> +Reference
> +[1] Si5341 Data Sheet
> + https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
> +
> +The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
> +clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
> +in turn can be directed to any of the 10 (or 4) outputs through a divider.
> +The internal structure of the clock generators can be found in [1].
> +
> +The driver can be used in "as is" mode, reading the current settings from the
> +chip at boot, in case you have a (pre-)programmed device. If the PLL is not
> +configured when the driver probes, it assumes the driver must fully initialize
> +it.
> +
> +The device type, speed grade and revision are determined runtime by probing.
> +
> +The driver currently only supports XTAL input mode, and does not support any
> +fancy input configurations. They can still be programmed into the chip and
> +the driver will leave them "as is".
> +
> +==I2C device node==
> +
> +Required properties:
> +- compatible: shall be one of the following: "silabs,si5341", "silabs,si5340"
One per line please.
> +- reg: i2c device address, usually 0x74
> +- #clock-cells: from common clock binding; shall be set to 1.
> +- clocks: from common clock binding; list of parent clock
> + handles, shall be xtal reference clock. Usually a fixed clock.
More indentation on the continued lines would help readability.
> +- clock-names: Shall be "xtal".
> +- #address-cells: shall be set to 1.
> +- #size-cells: shall be set to 0.
> +
> +Optional properties:
> +- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
> + feedback divider. Must be such that the PLL output is in the valid range. For
> + example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
> + the fraction matters, using 3500 and 12 will deliver the exact same result.
> + If these are not specified, and the PLL is not yet programmed when the driver
> + probes, the PLL will be set to 14GHz.
> +- silabs,reprogram: When present, the driver will always assume the device must
> + be initialized, and always performs the soft-reset routine. Since this will
> + temporarily stop all output clocks, don't do this if the chip is generating
> + the CPU clock for example.
I'm not too sure about this one. Seems like if you have child nodes,
then you should re-program. If you don't then you don't re-program.
> +
> +==Child nodes==
> +
> +Each of the clock outputs can be overwritten individually by
> +using a child node to the I2C device node. If a child node for a clock
> +output is not set, the configuration remains unchanged.
> +
> +Required child node properties:
> +- reg: number of clock output.
> +
> +Optional child node properties:
> +- silabs,format: Output format, see [1], 1=differential, 2=low-power, 4=LVCMOS
> +- silabs,common-mode: Output common mode, depends on standard.
Possible values?
> +- silabs,amplitude: Output amplitude, depends on standard.
> +- silabs,synth-source: Select which multisynth to use for this output
> +- silabs,synth-frequency: Sets the frequency for the multisynth connected to
> + this output. This will affect other outputs connected to this multisynth. The
> + setting is applied before silabs,synth-master and clock-frequency.
> +- silabs,synth-master: If present, this output is allowed to change the
> + multisynth frequency dynamically.
Boolean?
> +- clock-frequency: Sets a default frequency for this output.
range?
> +- always-on: Immediately and permanently enable this output. Particulary
Particularly
> + useful when combined with assigned-clocks, since that does not prepare clocks.
> +
> +==Example==
> +
> +/* 48MHz reference crystal */
> +ref48: ref48M {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <48000000>;
> +};
> +
> +i2c-master-node {
> +
> + /* Programmable clock (for logic) */
> + si5341: clock-generator@74 {
> + reg = <0x74>;
> + compatible = "silabs,si5341";
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&ref48>;
> + clock-names = "xtal";
> +
> + silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
> + silabs,pll-m-den = <48>;
> + silabs,reprogram; /* Chips are not programmed, always reset */
> +
> + /*
> + * Output 0 configuration:
> + * LVDS 3v3
> + * Source from Multisynth 3
> + * Use 600MHz synth frequency, and generate 100MHz from that
> + * Always keep this clock running
> + */
> + out0 {
clock@0
With a reg property, you should have a unit address.
> + /* refclk0 for PS-GT, usually for SATA or PCIe */
> + reg = <0>;
> + silabs,format = <1>; /* LVDS 3v3 */
> + silabs,common-mode = <3>;
> + silabs,amplitude = <3>;
> + silabs,synth-source = <3>; /* Multisynth 3 */
> + silabs,synth-frequency = <600000000>;
> + silabs,synth-master;
> + clock-frequency = <10000000>;
> + always-on;
> + };
> +
> + /*
> + * Output 6 configuration:
> + * LVDS 1v8
> + */
> + out6 {
> + /* FPGA clock 200MHz */
> + reg = <6>;
> + silabs,format = <1>; /* LVDS 1v8 */
> + silabs,common-mode = <13>;
> + silabs,amplitude = <3>;
> + };
> +
> + /*
> + * Output 8 configuration:
> + * HCSL 3v3
> + * run at 100MHz
> + */
> + out8 {
> + reg = <8>;
> + silabs,format = <2>;
> + silabs,common-mode = <11>;
> + silabs,amplitude = <3>;
> + silabs,synth-source = <0>;
> + clock-frequency = <100000000>;
> + };
> + };
> +};
> --
> 2.17.1
>
prev parent reply other threads:[~2019-05-02 0:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 9:02 [PATCH] dt-bindings: Add silabs,si5341 Mike Looijmans
2019-04-25 23:04 ` Stephen Boyd
2019-04-26 6:51 ` Mike Looijmans
2019-04-27 0:44 ` Stephen Boyd
2019-04-27 9:42 ` Mike Looijmans
2019-04-30 0:17 ` Stephen Boyd
2019-05-01 5:46 ` Mike Looijmans
2019-06-26 21:24 ` Stephen Boyd
2019-06-27 11:38 ` Mike Looijmans
2019-06-27 20:54 ` Stephen Boyd
2019-05-07 14:04 ` [PATCH v2] dt-bindings: clock: " Mike Looijmans
2019-05-13 20:31 ` Rob Herring
2019-05-17 13:20 ` [PATCH v3] " Mike Looijmans
2019-06-13 22:41 ` Rob Herring
2019-06-27 20:57 ` Stephen Boyd
2019-05-02 0:17 ` Rob Herring [this message]
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