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Fri, 10 May 2019 01:47:46 -0700 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , "Rob Herring" , Stephen Boyd CC: , , , , Joseph Lo Subject: [PATCH V3 8/8] arm64: tegra: Add external memory controller node for Tegra210 Date: Fri, 10 May 2019 16:47:19 +0800 Message-ID: <20190510084719.18902-9-josephl@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190510084719.18902-1-josephl@nvidia.com> References: <20190510084719.18902-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557478075; bh=eocGPlqW+n1IdvKSZMOFfDJJu3SXC+PU2zMU4nhYUVg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=fbamIRI/C594aLZxXFlIXqZwxfP2Xs7FkoUHrb06TIumF8oZN/F71D+Ph8w3xlYmO zWI87h8fzqsFxLLbnJsKujjzYkayOIEK6BurFy43vlM9TofjCrXkkY042XgPFu7e8n PJ/6A9UvePAhG7OEnE2qSwG7f031Ul+alPjbRyjuUwG51Nw5Yn/z/GQyCbh9oYhbtZ qmSjqtWO35r7k+sOXK+ASKB5GEk5BN747gwmujASQdqpyZp3GSGT22WItjAi7gdnUU maTuDTiF1u1zHO39g4R4GlITllvhh/zK53XMQJTC/RYGUSHnETDyFPiDWg5kf/h9AE zPluINnpkiaKg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add external memory controller (EMC) node for Tegra210 Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts= /nvidia/tegra210.dtsi index bc71ef8f9a09..b9ccfee39ed2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -872,6 +872,27 @@ #iommu-cells =3D <1>; }; =20 + external-memory-controller@7001b000 { + compatible =3D "nvidia,tegra210-emc"; + reg =3D <0x0 0x7001b000 0x0 0x1000>, + <0x0 0x7001e000 0x0 0x1000>, + <0x0 0x7001f000 0x0 0x1000>; + clocks =3D <&tegra_car TEGRA210_CLK_EMC>, + <&tegra_car TEGRA210_CLK_PLL_M>, + <&tegra_car TEGRA210_CLK_PLL_C>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_CLK_M>, + <&tegra_car TEGRA210_CLK_PLL_M_UD>, + <&tegra_car TEGRA210_CLK_PLL_MB_UD>, + <&tegra_car TEGRA210_CLK_PLL_MB>, + <&tegra_car TEGRA210_CLK_PLL_P_UD>; + clock-names =3D "emc", "pll_m", "pll_c", "pll_p", "clk_m", + "pll_m_ud", "pll_mb_ud", "pll_mb", "pll_p_ud"; + interrupts =3D ; + memory-region =3D <&emc_table>; + nvidia,memory-controller =3D <&mc>; + }; + sata@70020000 { compatible =3D "nvidia,tegra210-ahci"; reg =3D <0x0 0x70027000 0x0 0x2000>, /* AHCI */ @@ -1431,6 +1452,18 @@ }; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + emc_table: emc-table@8be00000 { + compatible =3D "nvidia,tegra210-emc-table"; + reg =3D <0x0 0x8be00000 0x0 0x10000>; + status =3D "disabled"; + }; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D