From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, sboyd@kernel.org,
b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, gregkh@linuxfoundation.org,
willy.mh.wolff.ml@gmail.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v10 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420
Date: Fri, 14 Jun 2019 11:52:57 +0200 [thread overview]
Message-ID: <20190614095309.24100-2-l.luba@partner.samsung.com> (raw)
In-Reply-To: <20190614095309.24100-1-l.luba@partner.samsung.com>
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469943f1..02d5ac469a3d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
+#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@@ -195,6 +196,16 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
+#define CLK_CLKM_PHY0 521
+#define CLK_CLKM_PHY1 522
+#define CLK_ACLK_PPMU_DREX0_0 523
+#define CLK_ACLK_PPMU_DREX0_1 524
+#define CLK_ACLK_PPMU_DREX1_0 525
+#define CLK_ACLK_PPMU_DREX1_1 526
+#define CLK_PCLK_PPMU_DREX0_0 527
+#define CLK_PCLK_PPMU_DREX0_1 528
+#define CLK_PCLK_PPMU_DREX1_0 529
+#define CLK_PCLK_PPMU_DREX1_1 530
/* mux clocks */
#define CLK_MOUT_HDMI 640
@@ -217,6 +228,8 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_SCLK_SPLL 660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -248,8 +261,11 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
+#define CLK_FF_DOUT_SPLL2 797
+#define CLK_DOUT_PCLK_DREX0 798
+#define CLK_DOUT_PCLK_DREX1 799
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 797
+#define CLK_NR_CLKS 800
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.17.1
next prev parent reply other threads:[~2019-06-14 9:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190614095319eucas1p2d47b6bd9179c7e4190972d6b22092ad7@eucas1p2.samsung.com>
2019-06-14 9:52 ` [PATCH v10 00/13] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190614095320eucas1p2919a6169c997bb81c80416e8a0ede538@eucas1p2.samsung.com>
2019-06-14 9:52 ` Lukasz Luba [this message]
2019-06-14 12:04 ` [PATCH v10 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Krzysztof Kozlowski
2019-06-14 12:38 ` Sylwester Nawrocki
2019-06-14 12:39 ` Krzysztof Kozlowski
[not found] ` <CGME20190614095321eucas1p2af62f3cdf78ba3c5a8013159da4f7502@eucas1p2.samsung.com>
2019-06-14 9:52 ` [PATCH v10 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
[not found] ` <CGME20190614095323eucas1p1312dd7bcc5a25cbb3af28ed0f52dc7a6@eucas1p1.samsung.com>
2019-06-14 9:52 ` [PATCH v10 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
[not found] ` <CGME20190614095324eucas1p2eab4def0ed8c912303e4bb3e422bb255@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 04/13] dt-bindings: ddr: rename lpddr2 directory Lukasz Luba
[not found] ` <CGME20190614095324eucas1p247ee87a9ca69733e7aebd601f5d96a94@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 05/13] dt-bindings: ddr: add LPDDR3 memories Lukasz Luba
[not found] ` <CGME20190614095325eucas1p20083d9290b36eca945ec3f1428bdbd4f@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 06/13] drivers: memory: extend of_memory by LPDDR3 support Lukasz Luba
2019-06-14 12:43 ` Krzysztof Kozlowski
2019-08-22 13:34 ` Lukasz Luba
2019-09-04 11:52 ` Greg KH
[not found] ` <CGME20190614095326eucas1p22e27d86d886d7a33acdd59c7f0f6d7d8@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
[not found] ` <CGME20190614095327eucas1p19b6e522efa15c8fd21c51f3900e376e9@eucas1p1.samsung.com>
2019-06-14 9:53 ` [PATCH v10 08/13] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-06-14 12:09 ` Krzysztof Kozlowski
2019-06-14 12:58 ` Krzysztof Kozlowski
2019-06-14 13:40 ` Lukasz Luba
2019-06-14 13:46 ` Krzysztof Kozlowski
2019-06-14 13:47 ` Krzysztof Kozlowski
2019-06-25 11:26 ` Lukasz Luba
[not found] ` <CGME20190614095328eucas1p24009b3a07322fd12e49eabb7a08baf50@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 09/13] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
2019-06-22 13:10 ` Chanwoo Choi
2019-06-25 7:31 ` Lukasz Luba
2019-06-25 7:38 ` Chanwoo Choi
[not found] ` <CGME20190614095329eucas1p267244e53d4f5612c46d6cc2c6bc0ed75@eucas1p2.samsung.com>
2019-06-14 9:53 ` [PATCH v10 10/13] ARM: dts: exynos: add chipid label and syscon compatible Lukasz Luba
[not found] ` <CGME20190614095330eucas1p1e5a73f31251af7d16caf951054ec9def@eucas1p1.samsung.com>
2019-06-14 9:53 ` [PATCH v10 11/13] ARM: dts: exynos: add syscon to clock compatible Lukasz Luba
[not found] ` <CGME20190614095331eucas1p138707301cac47902f0d0d9a41bd4a8a4@eucas1p1.samsung.com>
2019-06-14 9:53 ` [PATCH v10 12/13] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
[not found] ` <CGME20190614095332eucas1p10e0a690604c6210d5f61c55175532785@eucas1p1.samsung.com>
2019-06-14 9:53 ` [PATCH v10 13/13] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190614095309.24100-2-l.luba@partner.samsung.com \
--to=l.luba@partner.samsung.com \
--cc=b.zolnierkie@samsung.com \
--cc=cw00.choi@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=digetx@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=jroedel@suse.de \
--cc=keescook@chromium.org \
--cc=kgene@kernel.org \
--cc=krzk@kernel.org \
--cc=kyungmin.park@samsung.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=m.szyprowski@samsung.com \
--cc=mturquette@baylibre.com \
--cc=myungjoo.ham@samsung.com \
--cc=s.nawrocki@samsung.com \
--cc=sboyd@kernel.org \
--cc=tony@atomide.com \
--cc=treding@nvidia.com \
--cc=willy.mh.wolff.ml@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).