From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH 1/5] clk: renesas: rcar-gen2-legacy: Switch Z clock to .determine_rate()
Date: Mon, 17 Jun 2019 14:52:34 +0200 [thread overview]
Message-ID: <20190617125238.13761-2-geert+renesas@glider.be> (raw)
In-Reply-To: <20190617125238.13761-1-geert+renesas@glider.be>
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long. Hence switch the Z clock on R-Car Gen2 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.
This includes implementing range checking.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-rcar-gen2.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index da9fe3f032eb2a0d..f85837716d2840cf 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -66,19 +66,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
return div_u64((u64)parent_rate * mult, 32);
}
-static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int cpg_z_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- unsigned long prate = *parent_rate;
- unsigned int mult;
+ unsigned long prate = req->best_parent_rate;
+ unsigned int min_mult, max_mult, mult;
- if (!prate)
- prate = 1;
+ min_mult = max(div_u64(req->min_rate * 32ULL, prate), 1ULL);
+ max_mult = min(div_u64(req->max_rate * 32ULL, prate), 32ULL);
+ if (max_mult < min_mult)
+ return -EINVAL;
- mult = div_u64((u64)rate * 32, prate);
- mult = clamp(mult, 1U, 32U);
+ mult = div_u64(req->rate * 32ULL, prate);
+ mult = clamp(mult, min_mult, max_mult);
- return *parent_rate / 32 * mult;
+ req->rate = prate / 32 * mult;
+ return 0;
}
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -129,7 +132,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops cpg_z_clk_ops = {
.recalc_rate = cpg_z_clk_recalc_rate,
- .round_rate = cpg_z_clk_round_rate,
+ .determine_rate = cpg_z_clk_determine_rate,
.set_rate = cpg_z_clk_set_rate,
};
--
2.17.1
next prev parent reply other threads:[~2019-06-17 12:52 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-17 12:52 [PATCH 0/5] clk: renesas: rcar-gen2/gen3: Switch to .determine_rate() Geert Uytterhoeven
2019-06-17 12:52 ` Geert Uytterhoeven [this message]
2019-06-18 11:09 ` [PATCH 1/5] clk: renesas: rcar-gen2-legacy: Switch Z clock " Simon Horman
2019-08-30 8:43 ` Geert Uytterhoeven
2019-09-02 8:31 ` Simon Horman
2019-09-02 8:44 ` Geert Uytterhoeven
2019-09-05 8:22 ` Simon Horman
2019-06-17 12:52 ` [PATCH 2/5] clk: renesas: rcar-gen2: " Geert Uytterhoeven
2019-06-17 12:52 ` [PATCH 3/5] clk: renesas: rcar-gen3: Switch Z clocks " Geert Uytterhoeven
2019-06-17 12:52 ` [PATCH 4/5] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() Geert Uytterhoeven
2019-06-17 12:52 ` [PATCH 5/5] clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() Geert Uytterhoeven
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