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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id o126sm6802520wmo.1.2019.06.20.08.00.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Jun 2019 08:00:19 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com, khilman@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, martin.blumenstingl@googlemail.com, Neil Armstrong Subject: [RFC/RFT 00/14] arm64: g12a: add support for DVFS Date: Thu, 20 Jun 2019 16:59:59 +0200 Message-Id: <20190620150013.13462-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of the CPU clock in a safe way as recommended by the vendor Documentation and reference code. This patchset : - introduces needed core and meson clk changes - adds support for the G12B second cluster clock measurer ids - protects clock measurer from cooncurent measures - adds the clock notifiers - moves the G12A DT to a common g12a-common dtsi - adds the G12A and G12B OPPs - enables DVFS on all supported boards Dependencies: - PWM AO input order fix at [1] - PWM enhancements from Martin at [2] [1] https://patchwork.kernel.org/patch/11006835/ [2] https://patchwork.kernel.org/patch/11006835/ Neil Armstrong (14): pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux clk: core: introduce clk_hw_set_parent() clk: meson: regmap: export regmap_div ops functions clk: meson: eeclk: add setup callback soc: amlogic: meson-clk-measure: protect measure with a mutex soc: amlogic: meson-clk-measure: add G12B second cluster cpu clk clk: meson: g12a: add notifiers to handle cpu clock change clk: meson: g12a: expose CPUB clock ID for G12B arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux arm64: dts: meson-g12a: add cpus OPP table arm64: dts: meson-g12a: enable DVFS on G12A boards arm64: dts: meson-g12b: add cpus OPP tables arm64: dts: meson-g12b-odroid-n2: enable DVFS .../boot/dts/amlogic/meson-g12-common.dtsi | 2464 +++++++++++++++++ .../boot/dts/amlogic/meson-g12a-sei510.dts | 55 + .../boot/dts/amlogic/meson-g12a-u200.dts | 55 + .../boot/dts/amlogic/meson-g12a-x96-max.dts | 52 + arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 2462 +--------------- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 96 + arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 141 +- drivers/clk/clk.c | 5 + drivers/clk/meson/clk-regmap.c | 10 +- drivers/clk/meson/clk-regmap.h | 5 + drivers/clk/meson/g12a.c | 500 +++- drivers/clk/meson/meson-eeclk.c | 6 + drivers/clk/meson/meson-eeclk.h | 1 + drivers/pinctrl/meson/pinctrl-meson-g12a.c | 9 + drivers/soc/amlogic/meson-clk-measure.c | 14 +- include/dt-bindings/clock/g12a-clkc.h | 1 + include/linux/clk-provider.h | 1 + 17 files changed, 3412 insertions(+), 2465 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -- 2.21.0