From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB1E2C742D7 for ; Sat, 13 Jul 2019 03:47:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BCBC420830 for ; Sat, 13 Jul 2019 03:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727566AbfGMDrL (ORCPT ); Fri, 12 Jul 2019 23:47:11 -0400 Received: from hermes.aosc.io ([199.195.250.187]:42637 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727466AbfGMDrL (ORCPT ); Fri, 12 Jul 2019 23:47:11 -0400 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id E474F6EA60; Sat, 13 Jul 2019 03:47:04 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Date: Sat, 13 Jul 2019 11:46:26 +0800 Message-Id: <20190713034634.44585-1-icenowy@aosc.io> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patchset tries to add support for Allwinner V3/S3L and Sochip S3. Allwinner V3/V3s/S3L and Sochip S3 share the same die, but with different package. V3 is BGA w/o co-packaged DDR, V3s is QFP w/ DDR2, S3L is BGA w/ DDR2 and S3 is BGA w/ DDR3. (S3 and S3L is compatible for pinout, but because of different DDR, DDR voltage is different between the two variants). Because of the pin count of V3s is restricted due to the package, some pins are not bound on V3s, but they're bound on V3/S3/S3L. Currently the kernel is only prepared for the features available on V3s. This patchset adds the features missing on V3s for using them on V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by Sipeed, called Lichee Zero Plus. Icenowy Zheng (8): pinctrl: sunxi: v3s: introduce support for V3 clk: sunxi-ng: v3s: add the missing PLL_DDR1 dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks clk: sunxi-ng: v3s: add Allwinner V3 support ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 .../devicetree/bindings/arm/sunxi.yaml | 5 + .../clock/allwinner,sun4i-a10-ccu.yaml | 1 + arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 + .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++ arch/arm/boot/dts/sun8i-s3.dtsi | 6 + arch/arm/boot/dts/sun8i-s3l.dtsi | 6 + arch/arm/boot/dts/sun8i-v3.dtsi | 14 + drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 250 ++++++++++++++++- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 +- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265 +++++++++++++++++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 + include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 + 14 files changed, 604 insertions(+), 13 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi -- 2.21.0