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From: Icenowy Zheng <icenowy@aosc.io>
To: Rob Herring <robh+dt@kernel.org>,
	Maxime Ripard <maxime.ripard@bootlin.com>,
	Chen-Yu Tsai <wens@csie.org>,
	Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com,
	Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
Date: Sat, 13 Jul 2019 11:46:30 +0800
Message-ID: <20190713034634.44585-5-icenowy@aosc.io> (raw)
In-Reply-To: <20190713034634.44585-1-icenowy@aosc.io>

The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.

Fix this issue.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
New patch in v4.

 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 4eb68243e310..9c88015d4419 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
 		[CLK_MMC1]		= &mmc1_clk.common.hw,
 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
+		[CLK_MMC2]		= &mmc1_clk.common.hw,
+		[CLK_MMC2_SAMPLE]	= &mmc1_sample_clk.common.hw,
+		[CLK_MMC2_OUTPUT]	= &mmc1_output_clk.common.hw,
 		[CLK_CE]		= &ce_clk.common.hw,
 		[CLK_SPI0]		= &spi0_clk.common.hw,
 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
-- 
2.21.0


  parent reply index

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-13  3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-07-20  9:20   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-07-20  9:43   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-07-20  9:44   ` Maxime Ripard
2019-07-13  3:46 ` Icenowy Zheng [this message]
2019-07-20  9:44   ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Maxime Ripard
2019-07-20  9:45     ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-20  9:46   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-20  9:48   ` Maxime Ripard
2019-07-20  9:50     ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-15 17:03   ` Rob Herring
2019-07-20 10:13   ` Maxime Ripard
2019-07-20 11:39     ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-07-20 10:12   ` Maxime Ripard

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