* [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3
@ 2019-07-13 3:46 Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
` (7 more replies)
0 siblings, 8 replies; 25+ messages in thread
From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk,
linux-gpio, linux-sunxi, Icenowy Zheng
This patchset tries to add support for Allwinner V3/S3L and Sochip S3.
Allwinner V3/V3s/S3L and Sochip S3 share the same die, but with
different package. V3 is BGA w/o co-packaged DDR, V3s is QFP w/ DDR2,
S3L is BGA w/ DDR2 and S3 is BGA w/ DDR3. (S3 and S3L is compatible
for pinout, but because of different DDR, DDR voltage is different
between the two variants). Because of the pin count of V3s is
restricted due to the package, some pins are not bound on V3s, but
they're bound on V3/S3/S3L.
Currently the kernel is only prepared for the features available on V3s.
This patchset adds the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (8):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add the missing PLL_DDR1
dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
clk: sunxi-ng: v3s: add Allwinner V3 support
ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs
dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3
.../devicetree/bindings/arm/sunxi.yaml | 5 +
.../clock/allwinner,sun4i-a10-ccu.yaml | 1 +
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 +
.../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++
arch/arm/boot/dts/sun8i-s3.dtsi | 6 +
arch/arm/boot/dts/sun8i-s3l.dtsi | 6 +
arch/arm/boot/dts/sun8i-v3.dtsi | 14 +
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 250 ++++++++++++++++-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 +-
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265 +++++++++++++++++-
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
14 files changed, 604 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi
create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi
create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
--
2.21.0
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:20 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng ` (6 subsequent siblings) 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng Introduce the GPIO pins that is only available on V3 (not on V3s) to the V3s pinctrl driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v4: - Removed bogus alignment change. Changes in v3: - Fixed code alignment. - Fixed LVDS function number. Changes in v2: - Dropped the driver rename patch and apply the changes directly on V3s driver. drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265 +++++++++++++++++++++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + 2 files changed, 262 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 6704ce8e5e3d..ca85438e379a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -1,5 +1,5 @@ /* - * Allwinner V3s SoCs pinctrl driver. + * Allwinner V3/V3s SoCs pinctrl driver. * * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> * @@ -77,6 +77,30 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ SUNXI_FUNCTION(0x3, "uart0"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -98,6 +122,180 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ + /* Hole */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x4, "emac")), /* CRS */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */ + SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */ + SUNXI_FUNCTION(0x4, "emac")), /* MDC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */ + SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds")), /* VPC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds")), /* VNC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -291,6 +489,54 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ }; static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; @@ -305,13 +551,22 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun8i_v3s_pinctrl_data); + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); + + return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data, + variant); } static const struct of_device_id sun8i_v3s_pinctrl_match[] = { - { .compatible = "allwinner,sun8i-v3s-pinctrl", }, - {} + { + .compatible = "allwinner,sun8i-v3-pinctrl", + .data = (void *)PINCTRL_SUN8I_V3 + }, + { + .compatible = "allwinner,sun8i-v3s-pinctrl", + .data = (void *)PINCTRL_SUN8I_V3S + }, + { }, }; static struct platform_driver sun8i_v3s_pinctrl_driver = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 44e30deeee38..a32bb5bcb754 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -94,6 +94,8 @@ #define PINCTRL_SUN4I_A10 BIT(6) #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +#define PINCTRL_SUN8I_V3 BIT(9) +#define PINCTRL_SUN8I_V3S BIT(10) #define PIO_POW_MOD_SEL_REG 0x340 -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng @ 2019-07-20 9:20 ` Maxime Ripard 0 siblings, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:20 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi On Sat, Jul 13, 2019 at 11:46:27AM +0800, Icenowy Zheng wrote: > Introduce the GPIO pins that is only available on V3 (not on V3s) to the > V3s pinctrl driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:43 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng ` (5 subsequent siblings) 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot when developing the V3s CCU driver. Add back the missing PLL_DDR1. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes since v1. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 19 +++++++++++++++---- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 ++++-- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 9b3939fc7faa..4eb68243e310 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -77,7 +77,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", BIT(28), /* lock */ 0); -static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", "osc24M", 0x020, 8, 5, /* N */ 4, 2, /* K */ @@ -116,6 +116,14 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 2, /* post-div */ 0); +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7, /* N */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + static const char * const cpu_parents[] = { "osc32k", "osc24M", "pll-cpu", "pll-cpu" }; static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, @@ -303,7 +311,8 @@ static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0cc, BIT(16), 0); -static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" }; +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1", + "pll-periph0-2x" }; static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); @@ -363,10 +372,11 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = { &pll_audio_base_clk.common, &pll_video_clk.common, &pll_ve_clk.common, - &pll_ddr_clk.common, + &pll_ddr0_clk.common, &pll_periph0_clk.common, &pll_isp_clk.common, &pll_periph1_clk.common, + &pll_ddr1_clk.common, &cpu_clk.common, &axi_clk.common, &ahb1_clk.common, @@ -460,11 +470,12 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, [CLK_PLL_VE] = &pll_ve_clk.common.hw, - [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, [CLK_PLL_ISP] = &pll_isp_clk.common.hw, [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, [CLK_CPU] = &cpu_clk.common.hw, [CLK_AXI] = &axi_clk.common.hw, [CLK_AHB1] = &ahb1_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index fbc1da8b4520..10af324bd6b1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -20,7 +20,7 @@ #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO 6 #define CLK_PLL_VE 7 -#define CLK_PLL_DDR 8 +#define CLK_PLL_DDR0 8 #define CLK_PLL_PERIPH0 9 #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_ISP 11 @@ -49,6 +49,8 @@ /* And the GPU module clock is exported */ -#define CLK_NUMBER (CLK_MIPI_CSI + 1) +#define CLK_PLL_DDR1 74 + +#define CLK_NUMBER (CLK_PLL_DDR1 + 1) #endif /* _CCU_SUN8I_H3_H_ */ -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng @ 2019-07-20 9:43 ` Maxime Ripard 0 siblings, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:43 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 441 bytes --] On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote: > The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot > when developing the V3s CCU driver. > > Add back the missing PLL_DDR1. > > Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> queued for 5.4, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:44 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng ` (4 subsequent siblings) 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng, Rob Herring Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S) is only available on V3, and thus the clocks is not declared for V3s CCU. Add a V3 CCU compatible string to the binding to prepare for a CCU driver that provide I2S clock on V3, but not on V3s. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Rob Herring <robh@kernel.org> --- No changes since v3. Changes in v2: - Adapt to YAML binding document in linux-next. .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index c935405458fe..1bde87fc94c5 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -31,6 +31,7 @@ properties: - allwinner,sun8i-h3-ccu - allwinner,sun8i-h3-r-ccu - allwinner,sun8i-r40-ccu + - allwinner,sun8i-v3-ccu - allwinner,sun8i-v3s-ccu - allwinner,sun9i-a80-ccu - allwinner,sun50i-a64-ccu -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU 2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng @ 2019-07-20 9:44 ` Maxime Ripard 0 siblings, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:44 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Rob Herring [-- Attachment #1: Type: text/plain, Size: 553 bytes --] On Sat, Jul 13, 2019 at 11:46:29AM +0800, Icenowy Zheng wrote: > Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S) > is only available on V3, and thus the clocks is not declared for V3s > CCU. > > Add a V3 CCU compatible string to the binding to prepare for a CCU > driver that provide I2S clock on V3, but not on V3s. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Reviewed-by: Rob Herring <robh@kernel.org> Queued for 5.4, thanks Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng ` (2 preceding siblings ...) 2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:44 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng ` (3 subsequent siblings) 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng The MMC2 clock slices are currently not defined in V3s CCU driver, which makes MMC2 not working. Fix this issue. Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- New patch in v4. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 4eb68243e310..9c88015d4419 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { [CLK_MMC1] = &mmc1_clk.common.hw, [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc1_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks 2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng @ 2019-07-20 9:44 ` Maxime Ripard 2019-07-20 9:45 ` Icenowy Zheng 0 siblings, 1 reply; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:44 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1182 bytes --] On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote: > The MMC2 clock slices are currently not defined in V3s CCU driver, which > makes MMC2 not working. > > Fix this issue. > > Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > New patch in v4. > > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > index 4eb68243e310..9c88015d4419 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c > @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { > [CLK_MMC1] = &mmc1_clk.common.hw, > [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, > [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, > + [CLK_MMC2] = &mmc1_clk.common.hw, > + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, > + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, You're using the same structures than mmc1, I guess it's a copy and paste mistake? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks 2019-07-20 9:44 ` Maxime Ripard @ 2019-07-20 9:45 ` Icenowy Zheng 0 siblings, 0 replies; 25+ messages in thread From: Icenowy Zheng @ 2019-07-20 9:45 UTC (permalink / raw) To: Maxime Ripard Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi 于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote: >> The MMC2 clock slices are currently not defined in V3s CCU driver, >which >> makes MMC2 not working. >> >> Fix this issue. >> >> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU") >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> New patch in v4. >> >> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> index 4eb68243e310..9c88015d4419 100644 >> --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c >> @@ -513,6 +513,9 @@ static struct clk_hw_onecell_data >sun8i_v3s_hw_clks = { >> [CLK_MMC1] = &mmc1_clk.common.hw, >> [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, >> [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, >> + [CLK_MMC2] = &mmc1_clk.common.hw, >> + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, >> + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, > >You're using the same structures than mmc1, I guess it's a copy and >paste mistake? Yes. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com -- 使用 K-9 Mail 发送自我的Android设备。 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng ` (3 preceding siblings ...) 2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:46 ` Maxime Ripard 2019-07-22 17:07 ` Rob Herring 2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng ` (2 subsequent siblings) 7 siblings, 2 replies; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng Allwinner V3 has the same main die with V3s, but with more pins wired. There's a I2S bus on V3 that is not available on V3s. Add the V3-only peripheral's clocks and reset to the V3s CCU driver, bound to a new V3 compatible string. The driver name is not changed because it's part of the device tree binding (the header file name). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v4: - Add the missing MMC2 clock slices. No changes in v3/v2. drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +++++++++++++++++++++- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +- include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 + include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 + 4 files changed, 234 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 9c88015d4419..32854dec3753 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -235,6 +235,8 @@ static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 0x068, BIT(0), 0); static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x06c, BIT(0), 0); @@ -306,6 +308,11 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, BIT(31), /* gate */ 0); +static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", + "pll-audio-2x", "pll-audio" }; +static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, + 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); + static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0x0cc, BIT(8), 0); static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", @@ -443,6 +450,80 @@ static const struct clk_hw *clk_parent_pll_audio[] = { &pll_audio_base_clk.common.hw }; +static struct ccu_common *sun8i_v3_ccu_clks[] = { + &pll_cpu_clk.common, + &pll_audio_base_clk.common, + &pll_video_clk.common, + &pll_ve_clk.common, + &pll_ddr0_clk.common, + &pll_periph0_clk.common, + &pll_isp_clk.common, + &pll_periph1_clk.common, + &pll_ddr1_clk.common, + &cpu_clk.common, + &axi_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &ahb2_clk.common, + &bus_ce_clk.common, + &bus_dma_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_dram_clk.common, + &bus_emac_clk.common, + &bus_hstimer_clk.common, + &bus_spi0_clk.common, + &bus_otg_clk.common, + &bus_ehci0_clk.common, + &bus_ohci0_clk.common, + &bus_ve_clk.common, + &bus_tcon0_clk.common, + &bus_csi_clk.common, + &bus_de_clk.common, + &bus_codec_clk.common, + &bus_pio_clk.common, + &bus_i2s0_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_ephy_clk.common, + &bus_dbg_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc2_sample_clk.common, + &mmc2_output_clk.common, + &ce_clk.common, + &spi0_clk.common, + &i2s0_clk.common, + &usb_phy0_clk.common, + &usb_ohci0_clk.common, + &dram_clk.common, + &dram_ve_clk.common, + &dram_csi_clk.common, + &dram_ohci_clk.common, + &dram_ehci_clk.common, + &de_clk.common, + &tcon_clk.common, + &csi_misc_clk.common, + &csi0_mclk_clk.common, + &csi1_sclk_clk.common, + &csi1_mclk_clk.common, + &ve_clk.common, + &ac_dig_clk.common, + &avs_clk.common, + &mbus_clk.common, + &mipi_csi_clk.common, +}; + /* We hardcode the divider to 4 for now */ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", clk_parent_pll_audio, @@ -540,6 +621,88 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { .num = CLK_NUMBER, }; +static struct clk_hw_onecell_data sun8i_v3_hw_clks = { + .hws = { + [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.hw, + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_ISP] = &pll_isp_clk.common.hw, + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, + [CLK_CPU] = &cpu_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_AHB2] = &ahb2_clk.common.hw, + [CLK_BUS_CE] = &bus_ce_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_DE] = &bus_de_clk.common.hw, + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc1_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_CE] = &ce_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_DRAM] = &dram_clk.common.hw, + [CLK_DRAM_VE] = &dram_ve_clk.common.hw, + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, + [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw, + [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_TCON0] = &tcon_clk.common.hw, + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, + [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, + [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw, + [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AC_DIG] = &ac_dig_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { [RST_USB_PHY0] = { 0x0cc, BIT(0) }, @@ -575,6 +738,42 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { [RST_BUS_UART2] = { 0x2d8, BIT(18) }, }; +static struct ccu_reset_map sun8i_v3_ccu_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + + [RST_MBUS] = { 0x0fc, BIT(31) }, + + [RST_BUS_CE] = { 0x2c0, BIT(5) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, + + [RST_BUS_VE] = { 0x2c4, BIT(0) }, + [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_DE] = { 0x2c4, BIT(12) }, + [RST_BUS_DBG] = { 0x2c4, BIT(31) }, + + [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, + + [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, +}; + static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { .ccu_clks = sun8i_v3s_ccu_clks, .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), @@ -585,7 +784,18 @@ static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), }; -static void __init sun8i_v3s_ccu_setup(struct device_node *node) +static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = { + .ccu_clks = sun8i_v3_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks), + + .hw_clks = &sun8i_v3_hw_clks, + + .resets = sun8i_v3_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets), +}; + +static void __init sun8i_v3_v3s_ccu_init(struct device_node *node, + const struct sunxi_ccu_desc *ccu_desc) { void __iomem *reg; u32 val; @@ -601,7 +811,21 @@ static void __init sun8i_v3s_ccu_setup(struct device_node *node) val &= ~GENMASK(19, 16); writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); - sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc); + sunxi_ccu_probe(node, reg, ccu_desc); +} + +static void __init sun8i_v3s_ccu_setup(struct device_node *node) +{ + sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc); +} + +static void __init sun8i_v3_ccu_setup(struct device_node *node) +{ + sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc); } + CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu", sun8i_v3s_ccu_setup); + +CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu", + sun8i_v3_ccu_setup); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index 10af324bd6b1..b0160d305a67 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -51,6 +51,6 @@ #define CLK_PLL_DDR1 74 -#define CLK_NUMBER (CLK_PLL_DDR1 + 1) +#define CLK_NUMBER (CLK_I2S0 + 1) #endif /* _CCU_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h index c0d5d5599c87..014ac6123d17 100644 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -104,4 +104,8 @@ #define CLK_MIPI_CSI 73 +/* Clocks not available on V3s */ +#define CLK_BUS_I2S0 75 +#define CLK_I2S0 76 + #endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h index b58ef21a2e18..b6790173afd6 100644 --- a/include/dt-bindings/reset/sun8i-v3s-ccu.h +++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h @@ -75,4 +75,7 @@ #define RST_BUS_UART1 50 #define RST_BUS_UART2 51 +/* Reset lines not available on V3s */ +#define RST_BUS_I2S0 52 + #endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support 2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng @ 2019-07-20 9:46 ` Maxime Ripard 2019-07-22 17:07 ` Rob Herring 1 sibling, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:46 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 484 bytes --] On Sat, Jul 13, 2019 at 11:46:31AM +0800, Icenowy Zheng wrote: > + [CLK_MMC1] = &mmc1_clk.common.hw, > + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, > + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, > + [CLK_MMC2] = &mmc1_clk.common.hw, > + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw, > + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw, And there's the same mistake here. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support 2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng 2019-07-20 9:46 ` Maxime Ripard @ 2019-07-22 17:07 ` Rob Herring 1 sibling, 0 replies; 25+ messages in thread From: Rob Herring @ 2019-07-22 17:07 UTC (permalink / raw) To: Icenowy Zheng Cc: Maxime Ripard, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng On Sat, 13 Jul 2019 11:46:31 +0800, Icenowy Zheng wrote: > Allwinner V3 has the same main die with V3s, but with more pins wired. > There's a I2S bus on V3 that is not available on V3s. > > Add the V3-only peripheral's clocks and reset to the V3s CCU driver, > bound to a new V3 compatible string. The driver name is not changed > because it's part of the device tree binding (the header file name). > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Changes in v4: > - Add the missing MMC2 clock slices. > > No changes in v3/v2. > > drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +++++++++++++++++++++- > drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +- > include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 + > include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 + > 4 files changed, 234 insertions(+), 3 deletions(-) > Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng ` (4 preceding siblings ...) 2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 9:48 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, but with more GPIO wired out of the package. Add DTSI files for these SoCs. The DTSI file for V3 just replaces the pinctrl compatible string, and the S3/S3L DTSI files just include the V3 DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes since v2. arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ 3 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi new file mode 100644 index 000000000000..0f41a25ecb30 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include "sun8i-v3.dtsi" diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi new file mode 100644 index 000000000000..0f41a25ecb30 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include "sun8i-v3.dtsi" diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi new file mode 100644 index 000000000000..6ae8645ade50 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include "sun8i-v3s.dtsi" + +&ccu { + compatible = "allwinner,sun8i-v3-ccu"; +}; + +&pio { + compatible = "allwinner,sun8i-v3-pinctrl"; +}; -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs 2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng @ 2019-07-20 9:48 ` Maxime Ripard 2019-07-20 9:50 ` Icenowy Zheng 0 siblings, 1 reply; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 9:48 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 2213 bytes --] On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote: > The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, > but with more GPIO wired out of the package. > > Add DTSI files for these SoCs. The DTSI file for V3 just replaces the > pinctrl compatible string, and the S3/S3L DTSI files just include the V3 > DTSI file. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v2. > > arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ > 3 files changed, 26 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi > new file mode 100644 > index 000000000000..6ae8645ade50 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-v3.dtsi > @@ -0,0 +1,14 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3s.dtsi" > + > +&ccu { > + compatible = "allwinner,sun8i-v3-ccu"; > +}; > + > +&pio { > + compatible = "allwinner,sun8i-v3-pinctrl"; > +}; Is there any difference between the S3, S3L and V3? If not, then we don't need all those DTSI, just add the v3 Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs 2019-07-20 9:48 ` Maxime Ripard @ 2019-07-20 9:50 ` Icenowy Zheng 0 siblings, 0 replies; 25+ messages in thread From: Icenowy Zheng @ 2019-07-20 9:50 UTC (permalink / raw) To: linux-arm-kernel, Maxime Ripard Cc: devicetree, Linus Walleij, linux-sunxi, linux-kernel, linux-gpio, Chen-Yu Tsai, Rob Herring, linux-clk 于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote: >> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, >> but with more GPIO wired out of the package. >> >> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the >> pinctrl compatible string, and the S3/S3L DTSI files just include the >V3 >> DTSI file. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> No changes since v2. >> >> arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ >> 3 files changed, 26 insertions(+) >> create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi >> >> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi >b/arch/arm/boot/dts/sun8i-s3.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi >b/arch/arm/boot/dts/sun8i-s3l.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi >b/arch/arm/boot/dts/sun8i-v3.dtsi >> new file mode 100644 >> index 000000000000..6ae8645ade50 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi >> @@ -0,0 +1,14 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3s.dtsi" >> + >> +&ccu { >> + compatible = "allwinner,sun8i-v3-ccu"; >> +}; >> + >> +&pio { >> + compatible = "allwinner,sun8i-v3-pinctrl"; >> +}; > >Is there any difference between the S3, S3L and V3? DRAM. This might be useful when we introduce DRAM DVFS. > >If not, then we don't need all those DTSI, just add the v3 But I agree with this now. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com -- 使用 K-9 Mail 发送自我的Android设备。 ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng ` (5 preceding siblings ...) 2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-15 17:03 ` Rob Herring 2019-07-20 10:13 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng 7 siblings, 2 replies; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng The Lichee Zero Plus is a core board made by Sipeed, with a microUSB connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. It has a gold finger connector for expansion, and UART is available from reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or Allwinner V3L SoCs. Add the device tree binding of the basic version of the core board -- w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes since v3. Patch introduced in v2. Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 000a00d12d6a..48c126a7a848 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -353,6 +353,11 @@ properties: - const: licheepi,licheepi-zero - const: allwinner,sun8i-v3s + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) + items: + - const: sipeed,lichee-zero-plus + - const: allwinner,sun8i-s3 + - description: Linksprite PCDuino items: - const: linksprite,a10-pcduino -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng @ 2019-07-15 17:03 ` Rob Herring 2019-07-20 10:13 ` Maxime Ripard 1 sibling, 0 replies; 25+ messages in thread From: Rob Herring @ 2019-07-15 17:03 UTC (permalink / raw) To: Icenowy Zheng Cc: Maxime Ripard, Chen-Yu Tsai, Linus Walleij, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-kernel, linux-clk, open list:GPIO SUBSYSTEM, linux-sunxi On Fri, Jul 12, 2019 at 9:49 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> Rob ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng 2019-07-15 17:03 ` Rob Herring @ 2019-07-20 10:13 ` Maxime Ripard 2019-07-20 11:39 ` Icenowy Zheng 1 sibling, 1 reply; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 10:13 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1481 bytes --] On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash. > It has a gold finger connector for expansion, and UART is available from > reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > Allwinner V3L SoCs. > > Add the device tree binding of the basic version of the core board -- > w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes since v3. > > Patch introduced in v2. > > Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml > index 000a00d12d6a..48c126a7a848 100644 > --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > @@ -353,6 +353,11 @@ properties: > - const: licheepi,licheepi-zero > - const: allwinner,sun8i-v3s > > + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash) > + items: > + - const: sipeed,lichee-zero-plus > + - const: allwinner,sun8i-s3 If the S3 is just a rebranded V3, then we should have the v3 compatile in that list too. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-20 10:13 ` Maxime Ripard @ 2019-07-20 11:39 ` Icenowy Zheng 2019-07-22 19:29 ` Maxime Ripard 0 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-20 11:39 UTC (permalink / raw) To: linux-arm-kernel, Maxime Ripard Cc: devicetree, Linus Walleij, linux-sunxi, linux-kernel, linux-gpio, Chen-Yu Tsai, Rob Herring, linux-clk 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI >Flash. >> It has a gold finger connector for expansion, and UART is available >from >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or >> Allwinner V3L SoCs. >> >> Add the device tree binding of the basic version of the core board -- >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> No changes since v3. >> >> Patch introduced in v2. >> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml >b/Documentation/devicetree/bindings/arm/sunxi.yaml >> index 000a00d12d6a..48c126a7a848 100644 >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml >> @@ -353,6 +353,11 @@ properties: >> - const: licheepi,licheepi-zero >> - const: allwinner,sun8i-v3s >> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI >Flash) >> + items: >> + - const: sipeed,lichee-zero-plus >> + - const: allwinner,sun8i-s3 > >If the S3 is just a rebranded V3, then we should have the v3 compatile >in that list too. S3 is V3 with copackaged DDR3 DRAM. It's pin incompatible w/ V3. > >Maxime > >-- >Maxime Ripard, Bootlin >Embedded Linux and Kernel engineering >https://bootlin.com -- 使用 K-9 Mail 发送自我的Android设备。 ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-20 11:39 ` Icenowy Zheng @ 2019-07-22 19:29 ` Maxime Ripard 2019-07-24 13:09 ` Icenowy Zheng 0 siblings, 1 reply; 25+ messages in thread From: Maxime Ripard @ 2019-07-22 19:29 UTC (permalink / raw) To: Icenowy Zheng Cc: linux-arm-kernel, devicetree, Linus Walleij, linux-sunxi, linux-kernel, linux-gpio, Chen-Yu Tsai, Rob Herring, linux-clk [-- Attachment #1: Type: text/plain, Size: 2094 bytes --] On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: > > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard <maxime.ripard@bootlin.com> 写到: > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI > >Flash. > >> It has a gold finger connector for expansion, and UART is available > >from > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > >> Allwinner V3L SoCs. > >> > >> Add the device tree binding of the basic version of the core board -- > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > >> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > >> --- > >> No changes since v3. > >> > >> Patch introduced in v2. > >> > >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml > >b/Documentation/devicetree/bindings/arm/sunxi.yaml > >> index 000a00d12d6a..48c126a7a848 100644 > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > >> @@ -353,6 +353,11 @@ properties: > >> - const: licheepi,licheepi-zero > >> - const: allwinner,sun8i-v3s > >> > >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI > >Flash) > >> + items: > >> + - const: sipeed,lichee-zero-plus > >> + - const: allwinner,sun8i-s3 > > > >If the S3 is just a rebranded V3, then we should have the v3 compatile > >in that list too. > > S3 is V3 with copackaged DDR3 DRAM. > > It's pin incompatible w/ V3. Does it matter though? If the only thing that changes is the package, we're not manipulating that, and any software that deals with the v3 can deal with the s3. Which is what the compatible is about. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-22 19:29 ` Maxime Ripard @ 2019-07-24 13:09 ` Icenowy Zheng 2019-07-24 14:14 ` Maxime Ripard 0 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-24 13:09 UTC (permalink / raw) To: Maxime Ripard Cc: devicetree, Linus Walleij, linux-kernel, linux-gpio, linux-sunxi, Rob Herring, Chen-Yu Tsai, linux-clk, linux-arm-kernel 在 2019-07-23 03:29，Maxime Ripard 写道： > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: >> >> >> 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard >> <maxime.ripard@bootlin.com> 写到: >> >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: >> >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB >> >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI >> >Flash. >> >> It has a gold finger connector for expansion, and UART is available >> >from >> >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or >> >> Allwinner V3L SoCs. >> >> >> >> Add the device tree binding of the basic version of the core board -- >> >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. >> >> >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> >> --- >> >> No changes since v3. >> >> >> >> Patch introduced in v2. >> >> >> >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ >> >> 1 file changed, 5 insertions(+) >> >> >> >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> index 000a00d12d6a..48c126a7a848 100644 >> >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml >> >> @@ -353,6 +353,11 @@ properties: >> >> - const: licheepi,licheepi-zero >> >> - const: allwinner,sun8i-v3s >> >> >> >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI >> >Flash) >> >> + items: >> >> + - const: sipeed,lichee-zero-plus >> >> + - const: allwinner,sun8i-s3 >> > >> >If the S3 is just a rebranded V3, then we should have the v3 compatile >> >in that list too. >> >> S3 is V3 with copackaged DDR3 DRAM. >> >> It's pin incompatible w/ V3. > > Does it matter though? > > If the only thing that changes is the package, we're not manipulating > that, and any software that deals with the v3 can deal with the > s3. Which is what the compatible is about. Okay. Should the S3 compatible be kept befoer the V3 one? > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board 2019-07-24 13:09 ` Icenowy Zheng @ 2019-07-24 14:14 ` Maxime Ripard 0 siblings, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-24 14:14 UTC (permalink / raw) To: Icenowy Zheng Cc: devicetree, Linus Walleij, linux-kernel, linux-gpio, linux-sunxi, Rob Herring, Chen-Yu Tsai, linux-clk, linux-arm-kernel On Wed, Jul 24, 2019 at 09:09:01PM +0800, Icenowy Zheng wrote: > 在 2019-07-23 03:29，Maxime Ripard 写道： > > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote: > > > > > > > > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard > > > <maxime.ripard@bootlin.com> 写到: > > > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote: > > > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB > > > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI > > > >Flash. > > > >> It has a gold finger connector for expansion, and UART is available > > > >from > > > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or > > > >> Allwinner V3L SoCs. > > > >> > > > >> Add the device tree binding of the basic version of the core board -- > > > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC. > > > >> > > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > >> --- > > > >> No changes since v3. > > > >> > > > >> Patch introduced in v2. > > > >> > > > >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ > > > >> 1 file changed, 5 insertions(+) > > > >> > > > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >b/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> index 000a00d12d6a..48c126a7a848 100644 > > > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > > > >> @@ -353,6 +353,11 @@ properties: > > > >> - const: licheepi,licheepi-zero > > > >> - const: allwinner,sun8i-v3s > > > >> > > > >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI > > > >Flash) > > > >> + items: > > > >> + - const: sipeed,lichee-zero-plus > > > >> + - const: allwinner,sun8i-s3 > > > > > > > >If the S3 is just a rebranded V3, then we should have the v3 compatile > > > >in that list too. > > > > > > S3 is V3 with copackaged DDR3 DRAM. > > > > > > It's pin incompatible w/ V3. > > > > Does it matter though? > > > > If the only thing that changes is the package, we're not manipulating > > that, and any software that deals with the v3 can deal with the > > s3. Which is what the compatible is about. > > Okay. Should the S3 compatible be kept befoer the V3 one? Yep, something like (in the DT) compatible = "sipeed,lichee-zero-plus", "allwinner,sun8i-s3", "allwinner,sun8i-v3" Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng ` (6 preceding siblings ...) 2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng @ 2019-07-13 3:46 ` Icenowy Zheng 2019-07-20 10:12 ` Maxime Ripard 7 siblings, 1 reply; 25+ messages in thread From: Icenowy Zheng @ 2019-07-13 3:46 UTC (permalink / raw) To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Linus Walleij Cc: devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi, Icenowy Zheng Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- No changes in v4. Changes in v3: - Drop common regulator DTSI usage and added vcc3v3 regulator. arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9159fa2cea90..e320460a952b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1114,6 +1114,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 000000000000..7d2f6b145190 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-s3.dtsi" +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi new file mode 100644 index 000000000000..2677d319fb29 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; -- 2.21.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng @ 2019-07-20 10:12 ` Maxime Ripard 0 siblings, 0 replies; 25+ messages in thread From: Maxime Ripard @ 2019-07-20 10:12 UTC (permalink / raw) To: Icenowy Zheng Cc: Rob Herring, Chen-Yu Tsai, Linus Walleij, devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-gpio, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 3335 bytes --] On Sat, Jul 13, 2019 at 11:46:34AM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > No changes in v4. > > Changes in v3: > - Drop common regulator DTSI usage and added vcc3v3 regulator. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++++++++++++++++++ > 3 files changed, 55 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 9159fa2cea90..e320460a952b 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1114,6 +1114,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" Why do we need to mention both the S3 and S3l in the name? What are the differences between the two, and why do you need to share a DTSI? > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..2677d319fb29 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; > + status = "okay"; How can it do OTG if there's no controlable VBUS? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-07-25 11:32 UTC | newest] Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng 2019-07-20 9:20 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng 2019-07-20 9:43 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng 2019-07-20 9:44 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng 2019-07-20 9:44 ` Maxime Ripard 2019-07-20 9:45 ` Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng 2019-07-20 9:46 ` Maxime Ripard 2019-07-22 17:07 ` Rob Herring 2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng 2019-07-20 9:48 ` Maxime Ripard 2019-07-20 9:50 ` Icenowy Zheng 2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng 2019-07-15 17:03 ` Rob Herring 2019-07-20 10:13 ` Maxime Ripard 2019-07-20 11:39 ` Icenowy Zheng 2019-07-22 19:29 ` Maxime Ripard 2019-07-24 13:09 ` Icenowy Zheng 2019-07-24 14:14 ` Maxime Ripard 2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng 2019-07-20 10:12 ` Maxime Ripard
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