From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Paul Cercueil <paul@crapouillou.net>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
Date: Wed, 07 Aug 2019 14:33:57 -0700 [thread overview]
Message-ID: <20190807213358.A62002186A@mail.kernel.org> (raw)
In-Reply-To: <20190701113606.4130-1-paul@crapouillou.net>
Quoting Paul Cercueil (2019-07-01 04:36:06)
> The code was setting the bit 21 of the CPCCR register to use a divider
> of 2 for the "pll half" clock, and clearing the bit to use a divider
> of 1.
>
> This is the opposite of how this register field works: a cleared bit
> means that the /2 divider is used, and a set bit means that the divider
> is 1.
>
> Restore the correct behaviour using the newly introduced .div_table
> field.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
Applied to clk-next. Does this need a fixes tag?
next prev parent reply other threads:[~2019-08-07 21:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-01 11:36 [PATCH] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly Paul Cercueil
2019-08-07 21:33 ` Stephen Boyd [this message]
2019-08-07 23:28 ` Paul Cercueil
2019-08-08 4:08 ` Stephen Boyd
2019-08-08 13:18 ` Paul Cercueil
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