From: Dmitry Osipenko <digetx@gmail.com> To: Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Joseph Lo <josephl@nvidia.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Peter De Schrijver <pdeschrijver@nvidia.com>, Prashant Gaikwad <pgaikwad@nvidia.com>, Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 10/15] dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller Date: Mon, 12 Aug 2019 00:00:38 +0300 Message-ID: <20190811210043.20122-11-digetx@gmail.com> (raw) In-Reply-To: <20190811210043.20122-1-digetx@gmail.com> Add binding for the NVIDIA Tegra30 SoC Memory Controller. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- .../memory-controllers/nvidia,tegra30-mc.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml new file mode 100644 index 000000000000..84fd57bcf0dc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 SoC Memory Controller + +maintainers: + - Dmitry Osipenko <digetx@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: | + Tegra30 Memory Controller architecturally consists of the following parts: + + Arbitration Domains, which can handle a single request or response per + clock from a group of clients. Typically, a system has a single Arbitration + Domain, but an implementation may divide the client space into multiple + Arbitration Domains to increase the effective system bandwidth. + + Protocol Arbiter, which manage a related pool of memory devices. A system + may have a single Protocol Arbiter or multiple Protocol Arbiters. + + Memory Crossbar, which routes request and responses between Arbitration + Domains and Protocol Arbiters. In the simplest version of the system, the + Memory Crossbar is just a pass through between a single Arbitration Domain + and a single Protocol Arbiter. + + Global Resources, which include things like configuration registers which + are shared across the Memory Subsystem. + + The Tegra30 Memory Controller handles memory requests from internal clients + and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 + SDRAMs. + +properties: + compatible: + const: nvidia,tegra30-mc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 900000000 + + nvidia,emem-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Values to be written to the EMEM register block. See section + "18.13.1 MC Registers" in the TRM. + items: + - description: MC_EMEM_ARB_CFG + - description: MC_EMEM_ARB_OUTSTANDING_REQ + - description: MC_EMEM_ARB_TIMING_RCD + - description: MC_EMEM_ARB_TIMING_RP + - description: MC_EMEM_ARB_TIMING_RC + - description: MC_EMEM_ARB_TIMING_RAS + - description: MC_EMEM_ARB_TIMING_FAW + - description: MC_EMEM_ARB_TIMING_RRD + - description: MC_EMEM_ARB_TIMING_RAP2PRE + - description: MC_EMEM_ARB_TIMING_WAP2PRE + - description: MC_EMEM_ARB_TIMING_R2R + - description: MC_EMEM_ARB_TIMING_W2W + - description: MC_EMEM_ARB_TIMING_R2W + - description: MC_EMEM_ARB_TIMING_W2R + - description: MC_EMEM_ARB_DA_TURNS + - description: MC_EMEM_ARB_DA_COVERS + - description: MC_EMEM_ARB_MISC0 + - description: MC_EMEM_ARB_RING1_THROTTLE + + required: + - clock-frequency + - nvidia,emem-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <1>; + #reset-cells = <1>; + + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + }; -- 2.22.0
next prev parent reply index Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-11 21:00 [PATCH v10 00/15] memory: tegra: Introduce Tegra30 EMC driver Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 01/15] clk: tegra20/30: Add custom EMC clock implementation Dmitry Osipenko 2019-08-12 23:12 ` Michał Mirosław 2019-08-13 2:36 ` Dmitry Osipenko 2019-08-21 16:46 ` Thierry Reding 2019-09-10 10:33 ` Stephen Boyd 2019-08-11 21:00 ` [PATCH v10 02/15] memory: tegra20-emc: Drop setting EMC rate to max on probe Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 03/15] memory: tegra20-emc: Adapt for clock driver changes Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 04/15] memory: tegra20-emc: Include io.h instead of iopoll.h Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 05/15] memory: tegra20-emc: Pre-configure debug register Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 06/15] memory: tegra20-emc: Print a brief info message about the timings Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 07/15] memory: tegra20-emc: Increase handshake timeout Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 08/15] memory: tegra20-emc: wait_for_completion_timeout() doesn't return error Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 09/15] dt-bindings: memory: tegra30: Convert to Tegra124 YAML Dmitry Osipenko 2019-08-12 19:53 ` Rob Herring 2019-08-12 19:54 ` Rob Herring 2019-08-12 20:19 ` Dmitry Osipenko 2019-08-11 21:00 ` Dmitry Osipenko [this message] 2019-08-12 19:55 ` [PATCH v10 10/15] dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller Rob Herring 2019-08-11 21:00 ` [PATCH v10 11/15] dt-bindings: memory: Add binding for NVIDIA Tegra30 External " Dmitry Osipenko 2019-08-12 19:56 ` Rob Herring 2019-08-11 21:00 ` [PATCH v10 12/15] memory: tegra: Introduce Tegra30 EMC driver Dmitry Osipenko 2019-10-05 16:28 ` Peter Geis 2019-10-09 8:52 ` Dmitry Osipenko 2019-11-15 12:54 ` Jon Hunter 2019-11-15 13:17 ` Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 13/15] memory: tegra: Ensure timing control debug features are disabled Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 14/15] memory: tegra: Consolidate registers definition into common header Dmitry Osipenko 2019-08-11 21:00 ` [PATCH v10 15/15] ARM: dts: tegra30: Add External Memory Controller node Dmitry Osipenko 2019-10-29 13:51 ` [PATCH v10 00/15] memory: tegra: Introduce Tegra30 EMC driver Thierry Reding
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