From: Stephen Boyd <sboyd@kernel.org>
To: Macpaul Lin <macpaul.lin@mediatek.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Mars Cheng <mars.cheng@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Owen Chen <owen.chen@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Ryder Lee <ryder.lee@mediatek.com>,
Sean Wang <sean.wang@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org
Cc: wsd_upstream@mediatek.com, CC Hwang <cc.hwang@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
devicetree@vger.kernel.org, linux-serial@vger.kernel.org,
linux-clk@vger.kernel.org, Macpaul Lin <macpaul.lin@mediatek.com>
Subject: Re: [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support
Date: Wed, 14 Aug 2019 17:27:20 -0700 [thread overview]
Message-ID: <20190815002721.A71C72083B@mail.kernel.org> (raw)
In-Reply-To: <1562924653-10056-6-git-send-email-macpaul.lin@mediatek.com>
Quoting Macpaul Lin (2019-07-12 02:43:41)
> diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c
> new file mode 100644
> index 000000000000..41f19343dfb9
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6765-audio.c
> @@ -0,0 +1,109 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <owen.chen@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
Please use SPDX tags.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c
> new file mode 100644
> index 000000000000..eb9ae1c2c99c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <owen.chen@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
SPDX tags.
> diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c
> new file mode 100644
> index 000000000000..f716a48a926d
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt6765.c
> @@ -0,0 +1,961 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <owen.chen@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
SPDX tags.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/syscon.h>
Is this used? Maybe I deleted it.
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
[...]
> +
> +static const char * const axi_parents[] = {
> + "clk26m",
> + "syspll_d7",
> + "syspll1_d4",
> + "syspll3_d2"
> +};
> +
> +static const char * const mem_parents[] = {
> + "clk26m",
> + "dmpll_ck",
> + "apll1_ck"
> +};
> +
> +static const char * const mm_parents[] = {
> + "clk26m",
> + "mmpll_ck",
> + "syspll1_d2",
> + "syspll_d5",
> + "syspll1_d4",
> + "univpll_d5",
> + "univpll1_d2",
> + "mmpll_d2"
> +};
> +
> +static const char * const scp_parents[] = {
> + "clk26m",
> + "syspll4_d2",
> + "univpll2_d2",
> + "syspll1_d2",
> + "univpll1_d2",
> + "syspll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const mfg_parents[] = {
> + "clk26m",
> + "mfgpll_ck",
> + "syspll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const atb_parents[] = {
> + "clk26m",
> + "syspll1_d4",
> + "syspll1_d2"
> +};
> +
> +static const char * const camtg_parents[] = {
> + "clk26m",
> + "usb20_192m_d8",
> + "univpll2_d8",
> + "usb20_192m_d4",
> + "univpll2_d32",
> + "usb20_192m_d16",
> + "usb20_192m_d32"
> +};
> +
> +static const char * const uart_parents[] = {
> + "clk26m",
> + "univpll2_d8"
> +};
> +
> +static const char * const spi_parents[] = {
> + "clk26m",
> + "syspll3_d2",
> + "syspll4_d2",
> + "syspll2_d4"
> +};
> +
> +static const char * const msdc5hclk_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "univpll1_d4",
> + "syspll2_d2"
> +};
> +
> +static const char * const msdc50_0_parents[] = {
> + "clk26m",
> + "msdcpll_ck",
> + "syspll2_d2",
> + "syspll4_d2",
> + "univpll1_d2",
> + "syspll1_d2",
> + "univpll_d5",
> + "univpll1_d4"
> +};
> +
> +static const char * const msdc30_1_parents[] = {
> + "clk26m",
> + "msdcpll_d2",
> + "univpll2_d2",
> + "syspll2_d2",
> + "syspll1_d4",
> + "univpll1_d4",
> + "usb20_192m_d4",
> + "syspll2_d4"
> +};
> +
> +static const char * const audio_parents[] = {
> + "clk26m",
> + "syspll3_d4",
> + "syspll4_d4",
> + "syspll1_d16"
> +};
> +
> +static const char * const aud_intbus_parents[] = {
> + "clk26m",
> + "syspll1_d4",
> + "syspll4_d2"
> +};
> +
> +static const char * const aud_1_parents[] = {
> + "clk26m",
> + "apll1_ck"
> +};
> +
> +static const char * const aud_engen1_parents[] = {
> + "clk26m",
> + "apll1_d2",
> + "apll1_d4",
> + "apll1_d8"
> +};
> +
> +static const char * const disp_pwm_parents[] = {
> + "clk26m",
> + "univpll2_d4",
> + "ulposc1_d2",
> + "ulposc1_d8"
> +};
> +
> +static const char * const sspm_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "syspll_d3"
> +};
> +
> +static const char * const dxcc_parents[] = {
> + "clk26m",
> + "syspll1_d2",
> + "syspll1_d4",
> + "syspll1_d8"
> +};
> +
> +static const char * const usb_top_parents[] = {
> + "clk26m",
> + "univpll3_d4"
> +};
> +
> +static const char * const spm_parents[] = {
> + "clk26m",
> + "syspll1_d8"
> +};
> +
> +static const char * const i2c_parents[] = {
> + "clk26m",
> + "univpll3_d4",
> + "univpll3_d2",
> + "syspll1_d8",
> + "syspll2_d8"
> +};
> +
> +static const char * const pwm_parents[] = {
> + "clk26m",
> + "univpll3_d4",
> + "syspll1_d8"
> +};
> +
> +static const char * const seninf_parents[] = {
> + "clk26m",
> + "univpll1_d4",
> + "univpll1_d2",
> + "univpll2_d2"
> +};
> +
> +static const char * const aes_fde_parents[] = {
> + "clk26m",
> + "msdcpll_ck",
> + "univpll_d3",
> + "univpll2_d2",
> + "univpll1_d2",
> + "syspll1_d2"
> +};
> +
> +static const char * const ulposc_parents[] = {
> + "clk26m",
> + "ulposc1_d4",
> + "ulposc1_d8",
> + "ulposc1_d16",
> + "ulposc1_d32"
> +};
> +
> +static const char * const camtm_parents[] = {
> + "clk26m",
> + "univpll1_d4",
> + "univpll1_d2",
> + "univpll2_d2"
> +};
> +
Can you migrate this driver to the new way of specifying clk parents?
That way we don't just have lists of strings.
> +#define INVALID_UPDATE_REG 0xFFFFFFFF
> +#define INVALID_UPDATE_SHIFT -1
> +#define INVALID_MUX_GATE -1
> +
> +static const struct mtk_mux top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
> + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
> + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
Please add a comment why CLK_IS_CRITICAL flag is used in each place.
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
> + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
> + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
> + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
> + CLK_CFG_UPDATE, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
> + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
> + CLK_CFG_UPDATE, 3),
[...]
> + }, {
> + .compatible = "mediatek,mt6765-topckgen",
> + .data = clk_mt6765_top_probe,
> + }, {
> + .compatible = "mediatek,mt6765-infracfg",
> + .data = clk_mt6765_ifr_probe,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static int clk_mt6765_probe(struct platform_device *pdev)
> +{
> + int (*clk_probe)(struct platform_device *d);
> + int r;
> +
> + clk_probe = of_device_get_match_data(&pdev->dev);
> + if (!clk_probe)
> + return -EINVAL;
> +
> + r = clk_probe(pdev);
> + if (r)
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt6765_drv = {
> + .probe = clk_mt6765_probe,
> + .driver = {
> + .name = "clk-mt6765",
> + .owner = THIS_MODULE,
Remove this line, platform_driver_register() should take care of it.
> + .of_match_table = of_match_clk_mt6765,
> + },
> +};
> +
next prev parent reply other threads:[~2019-08-15 0:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin
2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin
2019-07-24 20:45 ` Rob Herring
2019-07-12 9:43 ` [PATCH v6 2/8] dt-bindings: mediatek: Add smi dts binding " Macpaul Lin
2019-07-12 9:43 ` [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings Macpaul Lin
2019-12-14 23:40 ` Matthias Brugger
2019-07-12 9:43 ` [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs Macpaul Lin
2019-07-24 20:46 ` Rob Herring
2019-07-12 9:43 ` [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support Macpaul Lin
2019-08-15 0:27 ` Stephen Boyd [this message]
2019-08-15 13:44 ` Greg KH
2019-12-02 8:55 ` Owen Chen
2019-07-12 9:43 ` [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin
2019-12-14 23:40 ` Matthias Brugger
2019-12-16 8:45 ` Matthias Brugger
2019-07-12 9:43 ` [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support Macpaul Lin
2019-07-15 8:29 ` CK Hu
2019-07-12 9:43 ` [PATCH v6 8/8] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
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