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[217.31.177.236]) by smtp.gmail.com with ESMTPSA id m74sm1174676lje.72.2019.08.30.15.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 15:14:42 -0700 (PDT) Date: Sat, 31 Aug 2019 00:14:41 +0200 From: Niklas =?iso-8859-1?Q?S=F6derlund?= To: Geert Uytterhoeven Cc: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 4/8] clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() Message-ID: <20190830221441.GT8479@bigcity.dyn.berto.se> References: <20190830134515.11925-1-geert+renesas@glider.be> <20190830134515.11925-5-geert+renesas@glider.be> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20190830134515.11925-5-geert+renesas@glider.be> User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Geert, Thanks for your work. On 2019-08-30 15:45:11 +0200, Geert Uytterhoeven wrote: > cpg_sd_clock_round_rate() is the sole caller of cpg_sd_clock_calc_div(), > hence absorb the latter into the former. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund > --- > v2: > - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to > .determine_rate()". > --- > drivers/clk/renesas/rcar-gen3-cpg.c | 19 +++++-------------- > 1 file changed, 5 insertions(+), 14 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index 9f457411984b1ca4..12ea5c9a671de788 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -309,15 +309,15 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, > clock->div_table[clock->cur_div_idx].div); > } > > -static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, > - unsigned long rate, > - unsigned long parent_rate) > +static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long *parent_rate) > { > unsigned long calc_rate, diff, diff_min = ULONG_MAX; > + struct sd_clock *clock = to_sd_clock(hw); > unsigned int i, best_div = 0; > > for (i = 0; i < clock->div_num; i++) { > - calc_rate = DIV_ROUND_CLOSEST(parent_rate, > + calc_rate = DIV_ROUND_CLOSEST(*parent_rate, > clock->div_table[i].div); > diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; > if (diff < diff_min) { > @@ -326,16 +326,7 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, > } > } > > - return best_div; > -} > - > -static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, > - unsigned long *parent_rate) > -{ > - struct sd_clock *clock = to_sd_clock(hw); > - unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); > - > - return DIV_ROUND_CLOSEST(*parent_rate, div); > + return DIV_ROUND_CLOSEST(*parent_rate, best_div); > } > > static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, > -- > 2.17.1 > -- Regards, Niklas Söderlund