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From: "Niklas Söderlund" <niklas.soderlund@ragnatech.se>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2 5/8] clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
Date: Sat, 31 Aug 2019 00:23:07 +0200
Message-ID: <20190830222307.GU8479@bigcity.dyn.berto.se> (raw)
In-Reply-To: <20190830134515.11925-6-geert+renesas@glider.be>

Hi Geert,

Thanks for your patch.

On 2019-08-30 15:45:12 +0200, Geert Uytterhoeven wrote:
> cpg_sd_clock_round_rate() really needs the best rate, not the best
> divider.  Hence change the iteration to find the former, and get rid of
> the final division.
> 
> Add an out-of-range rate check while at it.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> v2:
>   - Split off from "clk: renesas: rcar-gen3: Switch SD clocks to
>     .determine_rate()".
> ---
>  drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
> index 12ea5c9a671de788..a612045cba7d97b7 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -312,21 +312,25 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
>  static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
>  				      unsigned long *parent_rate)
>  {
> -	unsigned long calc_rate, diff, diff_min = ULONG_MAX;
> +	unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
>  	struct sd_clock *clock = to_sd_clock(hw);
> -	unsigned int i, best_div = 0;
> +	unsigned long calc_rate, diff;
> +	unsigned int i;
>  
>  	for (i = 0; i < clock->div_num; i++) {
>  		calc_rate = DIV_ROUND_CLOSEST(*parent_rate,
>  					      clock->div_table[i].div);
>  		diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
>  		if (diff < diff_min) {
> -			best_div = clock->div_table[i].div;
> +			best_rate = calc_rate;
>  			diff_min = diff;
>  		}
>  	}
>  
> -	return DIV_ROUND_CLOSEST(*parent_rate, best_div);
> +	if (best_rate > LONG_MAX)
> +		return -EINVAL;
> +
> +	return best_rate;
>  }
>  
>  static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
> -- 
> 2.17.1
> 

-- 
Regards,
Niklas Söderlund

  reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 13:45 [PATCH v2 0/8] clk: renesas: rcar-gen2/gen3: Switch to .determine_rate() Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 1/8] clk: renesas: rcar-gen2: Improve arithmetic divisions Geert Uytterhoeven
2019-08-30 21:42   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 2/8] clk: renesas: rcar-gen3: " Geert Uytterhoeven
2019-08-30 21:57   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 3/8] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() Geert Uytterhoeven
2019-08-30 22:06   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 4/8] clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() Geert Uytterhoeven
2019-08-30 22:14   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 5/8] clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() Geert Uytterhoeven
2019-08-30 22:23   ` Niklas Söderlund [this message]
2019-08-30 13:45 ` [PATCH v2 6/8] clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 7/8] clk: renesas: rcar-gen3: Switch Z clocks " Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 8/8] clk: renesas: rcar-gen3: Switch SD " Geert Uytterhoeven
2019-09-03 22:09 ` [PATCH v2 0/8] clk: renesas: rcar-gen2/gen3: Switch " Stephen Boyd
2019-09-04  6:51   ` Geert Uytterhoeven
2019-09-11 16:24     ` Stephen Boyd

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