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From: Stephen Boyd <sboyd@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk <linux-clk@vger.kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v2 0/8] clk: renesas: rcar-gen2/gen3: Switch to .determine_rate()
Date: Wed, 11 Sep 2019 09:24:45 -0700
Message-ID: <20190911162445.F377E2085B@mail.kernel.org> (raw)
In-Reply-To: <CAMuHMdVxktbMUn-JCO6Oz8zgG5V+dLv=3cMompErU33DkBG=0w@mail.gmail.com>

Quoting Geert Uytterhoeven (2019-09-03 23:51:10)
> Hi Stephen,
> 
> On Wed, Sep 4, 2019 at 12:09 AM Stephen Boyd <sboyd@kernel.org> wrote:
> > Quoting Geert Uytterhoeven (2019-08-30 06:45:07)
> > > As the .round_rate() callback returns a long clock rate, it cannot
> > > return clock rates that do not fit in signed long, but do fit in
> > > unsigned long.  The newer .determine_rate() callback does not suffer
> > > from this limitation.  In addition, .determine_rate() provides the
> > > ability to specify a rate range.
> > >
> > > This patch series performs the customary preparatory cleanups, and
> > > switches the Z (CPU) and SD clocks in the R-Car Gen2 and Gen3 clock
> > > drivers from the .round_rate() to the .determine_rate() callback.
> > > Note that the "div6" clock driver hasn't been converted yet, so div6
> > > clocks still use .round_rate().
> > >
> > > Changes compared to v1[1]:
> > >   - Add preparatory arithmetic division improvements
> > >   - Split off cpg_sd_clock_calc_div() absorption and SD clock best rate
> > >     calculation,
> > >   - Use div_u64() for division by unsigned long,
> > >
> > > This has been tested on R-Car M2-W and various R-Car Gen3, and should
> > > have no behavioral impact.
> >
> > From what I recall the rate range code is broken but I can't remember
> > how. Anyway, I was just curious if you ran into any issues with that
> > code.
> 
> I didn't ran into any issues.  But please note that in all tested cases, the
> limits were 0 and ULONG_MAX anyway, so probably it didn't trigger the
> broken cases in the rate range code.
> 
> So, is it good to have .determine_rate() support in individual clock drivers
> now, or do you want me to postpone the last 3 patches of my series until the
> rate range code is fixed?
> 

It's fine to use .determine_rate() because we'll fix the problems in the
clk framework. So no concern from me here. Just curious if you ran into
any problems.


  reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 13:45 Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 1/8] clk: renesas: rcar-gen2: Improve arithmetic divisions Geert Uytterhoeven
2019-08-30 21:42   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 2/8] clk: renesas: rcar-gen3: " Geert Uytterhoeven
2019-08-30 21:57   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 3/8] clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() Geert Uytterhoeven
2019-08-30 22:06   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 4/8] clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() Geert Uytterhoeven
2019-08-30 22:14   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 5/8] clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() Geert Uytterhoeven
2019-08-30 22:23   ` Niklas Söderlund
2019-08-30 13:45 ` [PATCH v2 6/8] clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 7/8] clk: renesas: rcar-gen3: Switch Z clocks " Geert Uytterhoeven
2019-08-30 13:45 ` [PATCH v2 8/8] clk: renesas: rcar-gen3: Switch SD " Geert Uytterhoeven
2019-09-03 22:09 ` [PATCH v2 0/8] clk: renesas: rcar-gen2/gen3: Switch " Stephen Boyd
2019-09-04  6:51   ` Geert Uytterhoeven
2019-09-11 16:24     ` Stephen Boyd [this message]
2019-10-21  8:35       ` Geert Uytterhoeven

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