From: Jernej Skrabec <jernej.skrabec@siol.net>
To: mripard@kernel.org, wens@csie.org
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] clk: sunxi-ng: h6: Allow GPU to change parent rate
Date: Tue, 1 Oct 2019 22:06:56 +0200 [thread overview]
Message-ID: <20191001200656.730198-1-jernej.skrabec@siol.net> (raw)
GPU PLL was designed with dynamic frequency switching in mind so driver
can adjust rate based on the GPU load.
Allow GPU clock to change parent rate (GPU PLL is the only possible
parent of GPU clock).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index d89353a3cdec..e254c06c8621 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -290,7 +290,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
0, 3, /* M */
24, 1, /* mux */
BIT(31), /* gate */
- 0);
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
0x67c, BIT(0), 0);
--
2.23.0
next reply other threads:[~2019-10-01 20:07 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-01 20:06 Jernej Skrabec [this message]
2019-10-02 6:06 ` [PATCH] clk: sunxi-ng: h6: Allow GPU to change parent rate Maxime Ripard
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