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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id r13sm32913737wrn.0.2019.10.02.02.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 02:15:38 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong Cc: Jerome Brunet , Kevin Hilman , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/7] clk: meson: axg-audio: provide clk top signal name Date: Wed, 2 Oct 2019 11:15:28 +0200 Message-Id: <20191002091529.17112-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191002091529.17112-1-jbrunet@baylibre.com> References: <20191002091529.17112-1-jbrunet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The peripheral clock on the sm1 goes through some muxes and dividers before reaching the audio gates. To model that, without repeating our self too much, the "top" clock signal is introduced and will serve as a the parent of the gates. On the axg and g12a, the top clock is just a pass-through to the audio peripheral clock provided by the main controller. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-audio.c | 18 +++++++++++++++--- drivers/clk/meson/axg-audio.h | 3 ++- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index ce8836776d1c..1a4c50a29ad7 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -74,9 +74,7 @@ .hw.init = &(struct clk_init_data) { \ .name = "aud_"#_name, \ .ops = &clk_regmap_gate_ops, \ - .parent_data = &(const struct clk_parent_data) { \ - .fw_name = "pclk", \ - }, \ + .parent_names = (const char *[]){ "aud_top" }, \ .num_parents = 1, \ }, \ } @@ -504,6 +502,18 @@ static struct clk_regmap tdmout_c_lrclk = AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); /* AXG/G12A Clocks */ +static struct clk_hw axg_aud_top = { + .init = &(struct clk_init_data) { + /* Provide aud_top signal name on axg and g12a */ + .name = "aud_top", + .ops = &(const struct clk_ops) {}, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "pclk", + }, + .num_parents = 1, + }, +}; + static struct clk_regmap mst_a_mclk_sel = AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); static struct clk_regmap mst_b_mclk_sel = @@ -691,6 +701,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, + [AUD_CLKID_TOP] = &axg_aud_top, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -835,6 +846,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = { [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, + [AUD_CLKID_TOP] = &axg_aud_top, [NR_CLKS] = NULL, }, .num = NR_CLKS, diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index c00e28b2e1a9..a4956837f597 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -116,9 +116,10 @@ #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 + /* include the CLKIDs which are part of the DT bindings */ #include -#define NR_CLKS 163 +#define NR_CLKS 164 #endif /*__AXG_AUDIO_CLKC_H */ -- 2.21.0