From: Andrew Jeffery <andrew@aj.id.au>
To: linux-clk@vger.kernel.org
Cc: mturquette@baylibre.com, sboyd@kernel.org, joel@jms.id.au,
robh+dt@kernel.org, mark.rutland@arm.com,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
Date: Thu, 10 Oct 2019 12:36:55 +1030 [thread overview]
Message-ID: <20191010020655.3776-3-andrew@aj.id.au> (raw)
In-Reply-To: <20191010020655.3776-1-andrew@aj.id.au>
RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
v2: Drop "-gate" from clock names
drivers/clk/clk-aspeed.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index abf06fb6453e..411ff5fb2c07 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,7 @@
#include "clk-aspeed.h"
-#define ASPEED_NUM_CLKS 36
+#define ASPEED_NUM_CLKS 38
#define ASPEED_RESET2_OFFSET 32
@@ -28,6 +28,7 @@
#define AST2400_HPLL_BYPASS_EN BIT(17)
#define ASPEED_MISC_CTRL 0x2c
#define UART_DIV13_EN BIT(12)
+#define ASPEED_MAC_CLK_DLY 0x48
#define ASPEED_STRAP 0x70
#define CLKIN_25MHZ_EN BIT(23)
#define AST2400_CLK_SOURCE_SEL BIT(18)
@@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
+ if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
+ /* RMII 50MHz RCLK */
+ hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
+ 50000000);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ /* RMII1 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+ scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
+
+ /* RMII2 50MHz (RCLK) output enable */
+ hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+ scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
+ &aspeed_clk_lock);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
+ }
+
/* LPC Host (LHCLK) clock divider */
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
--
2.20.1
next prev parent reply other threads:[~2019-10-10 2:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-10 2:06 [PATCH v2 0/2] clk: aspeed: Expose RMII RCLK gate for MACs 1-2 on AST2500 Andrew Jeffery
2019-10-10 2:06 ` [PATCH v2 1/2] dt-bindings: clock: Add AST2500 RMII RCLK definitions Andrew Jeffery
2019-10-10 23:39 ` Joel Stanley
2019-10-11 17:01 ` Rob Herring
2019-10-10 2:06 ` Andrew Jeffery [this message]
2019-10-10 23:41 ` [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs Joel Stanley
2019-11-26 0:59 ` Joel Stanley
2019-11-26 18:01 ` Stephen Boyd
2019-11-26 18:03 ` Stephen Boyd
2019-11-29 1:22 ` Joel Stanley
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