* [PATCH v4 1/7] clk: actions: Fix factor clk struct member access
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-09-17 16:34 ` Stephen Boyd
2019-09-17 20:01 ` Stephen Boyd
2019-09-16 15:45 ` [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding Manivannan Sadhasivam
` (6 subsequent siblings)
7 siblings, 2 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Since the helper "owl_factor_helper_round_rate" is shared between factor
and composite clocks, using the factor clk specific helper function
like "hw_to_owl_factor" to access its members will create issues when
called from composite clk specific code. Hence, pass the "factor_hw"
struct pointer directly instead of fetching it using factor clk specific
helpers.
This issue has been observed when a composite clock like "sd0_clk" tried
to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
error.
While we are at it, let's rename the "clk_val_best" function to
"owl_clk_val_best" since this is an owl SoCs specific helper.
Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/actions/owl-factor.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c
index 317d4a9e112e..f15e2621fa18 100644
--- a/drivers/clk/actions/owl-factor.c
+++ b/drivers/clk/actions/owl-factor.c
@@ -64,11 +64,10 @@ static unsigned int _get_table_val(const struct clk_factor_table *table,
return val;
}
-static int clk_val_best(struct clk_hw *hw, unsigned long rate,
+static int owl_clk_val_best(const struct owl_factor_hw *factor_hw,
+ struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate)
{
- struct owl_factor *factor = hw_to_owl_factor(hw);
- struct owl_factor_hw *factor_hw = &factor->factor_hw;
const struct clk_factor_table *clkt = factor_hw->table;
unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
unsigned long parent_rate_saved = *best_parent_rate;
@@ -126,7 +125,7 @@ long owl_factor_helper_round_rate(struct owl_clk_common *common,
const struct clk_factor_table *clkt = factor_hw->table;
unsigned int val, mul = 0, div = 1;
- val = clk_val_best(&common->hw, rate, parent_rate);
+ val = owl_clk_val_best(factor_hw, &common->hw, rate, parent_rate);
_get_table_div_mul(clkt, val, &mul, &div);
return *parent_rate * mul / div;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 1/7] clk: actions: Fix factor clk struct member access
2019-09-16 15:45 ` [PATCH v4 1/7] clk: actions: Fix factor clk struct member access Manivannan Sadhasivam
@ 2019-09-17 16:34 ` Stephen Boyd
2019-09-17 16:36 ` Manivannan Sadhasivam
2019-09-17 20:01 ` Stephen Boyd
1 sibling, 1 reply; 21+ messages in thread
From: Stephen Boyd @ 2019-09-17 16:34 UTC (permalink / raw)
To: Manivannan Sadhasivam, afaerber, robh+dt, ulf.hansson
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Quoting Manivannan Sadhasivam (2019-09-16 08:45:40)
> Since the helper "owl_factor_helper_round_rate" is shared between factor
> and composite clocks, using the factor clk specific helper function
> like "hw_to_owl_factor" to access its members will create issues when
> called from composite clk specific code. Hence, pass the "factor_hw"
> struct pointer directly instead of fetching it using factor clk specific
> helpers.
>
> This issue has been observed when a composite clock like "sd0_clk" tried
> to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
> error.
>
> While we are at it, let's rename the "clk_val_best" function to
> "owl_clk_val_best" since this is an owl SoCs specific helper.
>
> Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> ---
I can apply this to clk-next?
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 1/7] clk: actions: Fix factor clk struct member access
2019-09-17 16:34 ` Stephen Boyd
@ 2019-09-17 16:36 ` Manivannan Sadhasivam
0 siblings, 0 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-17 16:36 UTC (permalink / raw)
To: Stephen Boyd
Cc: afaerber, robh+dt, ulf.hansson, linux-arm-kernel, linux-mmc,
linux-kernel, devicetree, thomas.liau, linux-actions,
linus.walleij, linux-clk
On Tue, Sep 17, 2019 at 09:34:18AM -0700, Stephen Boyd wrote:
> Quoting Manivannan Sadhasivam (2019-09-16 08:45:40)
> > Since the helper "owl_factor_helper_round_rate" is shared between factor
> > and composite clocks, using the factor clk specific helper function
> > like "hw_to_owl_factor" to access its members will create issues when
> > called from composite clk specific code. Hence, pass the "factor_hw"
> > struct pointer directly instead of fetching it using factor clk specific
> > helpers.
> >
> > This issue has been observed when a composite clock like "sd0_clk" tried
> > to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
> > error.
> >
> > While we are at it, let's rename the "clk_val_best" function to
> > "owl_clk_val_best" since this is an owl SoCs specific helper.
> >
> > Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> > ---
>
> I can apply this to clk-next?
Yes, please :-) Rest can go through Ulf's tree.
Thanks,
Mani
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 1/7] clk: actions: Fix factor clk struct member access
2019-09-16 15:45 ` [PATCH v4 1/7] clk: actions: Fix factor clk struct member access Manivannan Sadhasivam
2019-09-17 16:34 ` Stephen Boyd
@ 2019-09-17 20:01 ` Stephen Boyd
1 sibling, 0 replies; 21+ messages in thread
From: Stephen Boyd @ 2019-09-17 20:01 UTC (permalink / raw)
To: Manivannan Sadhasivam, afaerber, robh+dt, ulf.hansson
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Quoting Manivannan Sadhasivam (2019-09-16 08:45:40)
> Since the helper "owl_factor_helper_round_rate" is shared between factor
> and composite clocks, using the factor clk specific helper function
> like "hw_to_owl_factor" to access its members will create issues when
> called from composite clk specific code. Hence, pass the "factor_hw"
> struct pointer directly instead of fetching it using factor clk specific
> helpers.
>
> This issue has been observed when a composite clock like "sd0_clk" tried
> to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
> error.
>
> While we are at it, let's rename the "clk_val_best" function to
> "owl_clk_val_best" since this is an owl SoCs specific helper.
>
> Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
2019-09-16 15:45 ` [PATCH v4 1/7] clk: actions: Fix factor clk struct member access Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-09-16 18:00 ` Rob Herring
` (2 more replies)
2019-09-16 15:45 ` [PATCH v4 3/7] arm64: dts: actions: Add MMC controller support for S900 Manivannan Sadhasivam
` (5 subsequent siblings)
7 siblings, 3 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Add devicetree YAML binding for Actions Semi Owl SoC's SD/MMC/SDIO
controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../devicetree/bindings/mmc/owl-mmc.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
new file mode 100644
index 000000000000..12b40213426d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl SoCs SD/MMC/SDIO controller
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ compatible:
+ const: actions,owl-mmc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: mmc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - dmas
+ - dma-names
+
+examples:
+ - |
+ mmc0: mmc@e0330000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe0330000 0x0 0x4000>;
+ interrupts = <0 42 4>;
+ clocks = <&cmu 56>;
+ resets = <&cmu 23>;
+ dmas = <&dma 2>;
+ dma-names = "mmc";
+ bus-width = <4>;
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
2019-09-16 15:45 ` [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding Manivannan Sadhasivam
@ 2019-09-16 18:00 ` Rob Herring
2019-09-16 22:57 ` Linus Walleij
2019-10-03 10:01 ` Ulf Hansson
2 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2019-09-16 18:00 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Ulf Hansson, Andreas Färber, Stephen Boyd,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-mmc, linux-kernel, devicetree, Thomas Liau, linux-actions,
Linus Walleij, linux-clk
On Mon, Sep 16, 2019 at 10:46 AM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Add devicetree YAML binding for Actions Semi Owl SoC's SD/MMC/SDIO
> controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../devicetree/bindings/mmc/owl-mmc.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
2019-09-16 15:45 ` [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding Manivannan Sadhasivam
2019-09-16 18:00 ` Rob Herring
@ 2019-09-16 22:57 ` Linus Walleij
2019-10-03 10:01 ` Ulf Hansson
2 siblings, 0 replies; 21+ messages in thread
From: Linus Walleij @ 2019-09-16 22:57 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Ulf Hansson, Andreas Färber, Rob Herring, Stephen Boyd,
Linux ARM, linux-mmc, linux-kernel,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Thomas C. Liau, linux-actions, linux-clk
On Mon, Sep 16, 2019 at 5:46 PM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add devicetree YAML binding for Actions Semi Owl SoC's SD/MMC/SDIO
> controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Neat use of yaml!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
2019-09-16 15:45 ` [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding Manivannan Sadhasivam
2019-09-16 18:00 ` Rob Herring
2019-09-16 22:57 ` Linus Walleij
@ 2019-10-03 10:01 ` Ulf Hansson
2 siblings, 0 replies; 21+ messages in thread
From: Ulf Hansson @ 2019-10-03 10:01 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Andreas Färber, Rob Herring, Stephen Boyd, Linux ARM,
linux-mmc, Linux Kernel Mailing List, DTML, thomas.liau,
linux-actions, Linus Walleij, linux-clk
On Mon, 16 Sep 2019 at 17:46, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Add devicetree YAML binding for Actions Semi Owl SoC's SD/MMC/SDIO
> controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> .../devicetree/bindings/mmc/owl-mmc.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> new file mode 100644
> index 000000000000..12b40213426d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Actions Semi Owl SoCs SD/MMC/SDIO controller
> +
> +allOf:
> + - $ref: "mmc-controller.yaml"
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +properties:
> + compatible:
> + const: actions,owl-mmc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 1
> +
> + dma-names:
> + const: mmc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - resets
> + - dmas
> + - dma-names
> +
> +examples:
> + - |
> + mmc0: mmc@e0330000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0330000 0x0 0x4000>;
> + interrupts = <0 42 4>;
> + clocks = <&cmu 56>;
> + resets = <&cmu 23>;
> + dmas = <&dma 2>;
> + dma-names = "mmc";
> + bus-width = <4>;
> + };
> +
> +...
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 3/7] arm64: dts: actions: Add MMC controller support for S900
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
2019-09-16 15:45 ` [PATCH v4 1/7] clk: actions: Fix factor clk struct member access Manivannan Sadhasivam
2019-09-16 15:45 ` [PATCH v4 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-10-14 14:44 ` Manivannan Sadhasivam
2019-09-16 15:45 ` [PATCH v4 4/7] arm64: dts: actions: Add uSD and eMMC support for Bubblegum96 Manivannan Sadhasivam
` (4 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Add MMC controller support for Actions Semi S900 SoC. There are 4 MMC
controllers in this SoC which can be used for accessing SD/MMC/SDIO cards.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/actions/s900.dtsi | 45 +++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index df3a68a3ac97..eb35cf78ab73 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/actions,s900-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/actions,s900-reset.h>
@@ -284,5 +285,49 @@
dma-requests = <46>;
clocks = <&cmu CLK_DMAC>;
};
+
+ mmc0: mmc@e0330000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe0330000 0x0 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD0>;
+ resets = <&cmu RESET_SD0>;
+ dmas = <&dma 2>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc1: mmc@e0334000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe0334000 0x0 0x4000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD1>;
+ resets = <&cmu RESET_SD1>;
+ dmas = <&dma 3>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc2: mmc@e0338000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe0338000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD2>;
+ resets = <&cmu RESET_SD2>;
+ dmas = <&dma 4>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc3: mmc@e033c000 {
+ compatible = "actions,owl-mmc";
+ reg = <0x0 0xe033c000 0x0 0x4000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD3>;
+ resets = <&cmu RESET_SD3>;
+ dmas = <&dma 46>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 3/7] arm64: dts: actions: Add MMC controller support for S900
2019-09-16 15:45 ` [PATCH v4 3/7] arm64: dts: actions: Add MMC controller support for S900 Manivannan Sadhasivam
@ 2019-10-14 14:44 ` Manivannan Sadhasivam
0 siblings, 0 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-10-14 14:44 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk
On Mon, Sep 16, 2019 at 09:15:42PM +0530, Manivannan Sadhasivam wrote:
> Add MMC controller support for Actions Semi S900 SoC. There are 4 MMC
> controllers in this SoC which can be used for accessing SD/MMC/SDIO cards.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for v5.5.
Thanks,
Mani
> ---
> arch/arm64/boot/dts/actions/s900.dtsi | 45 +++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
> index df3a68a3ac97..eb35cf78ab73 100644
> --- a/arch/arm64/boot/dts/actions/s900.dtsi
> +++ b/arch/arm64/boot/dts/actions/s900.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/actions,s900-cmu.h>
> +#include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/actions,s900-reset.h>
>
> @@ -284,5 +285,49 @@
> dma-requests = <46>;
> clocks = <&cmu CLK_DMAC>;
> };
> +
> + mmc0: mmc@e0330000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0330000 0x0 0x4000>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD0>;
> + resets = <&cmu RESET_SD0>;
> + dmas = <&dma 2>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@e0334000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0334000 0x0 0x4000>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD1>;
> + resets = <&cmu RESET_SD1>;
> + dmas = <&dma 3>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc2: mmc@e0338000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0338000 0x0 0x4000>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD2>;
> + resets = <&cmu RESET_SD2>;
> + dmas = <&dma 4>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc3: mmc@e033c000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe033c000 0x0 0x4000>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD3>;
> + resets = <&cmu RESET_SD3>;
> + dmas = <&dma 46>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> };
> };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 4/7] arm64: dts: actions: Add uSD and eMMC support for Bubblegum96
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
` (2 preceding siblings ...)
2019-09-16 15:45 ` [PATCH v4 3/7] arm64: dts: actions: Add MMC controller support for S900 Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-10-14 14:45 ` Manivannan Sadhasivam
2019-09-16 15:45 ` [PATCH v4 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver Manivannan Sadhasivam
` (3 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Add uSD and eMMC support for Bubblegum96 board based on Actions Semi
S900 SoC. SD0 is connected to uSD slot and SD2 is connected to eMMC.
Since there is no PMIC support added yet, fixed regulator has been
used as a regulator node.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
.../boot/dts/actions/s900-bubblegum-96.dts | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index 732daaa6e9d3..59291e0ea1ee 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -12,6 +12,9 @@
model = "Bubblegum-96";
aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &mmc2;
serial5 = &uart5;
};
@@ -23,6 +26,24 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ /* Fixed regulator used in the absence of PMIC */
+ vcc_3v1: vcc-3v1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.1V";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
+
+ /* Fixed regulator used in the absence of PMIC */
+ sd_vcc: sd-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.1V";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
};
&i2c0 {
@@ -241,6 +262,47 @@
bias-pull-up;
};
};
+
+ mmc0_default: mmc0_default {
+ pinmux {
+ groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
+ "sd0_cmd_mfp", "sd0_clk_mfp";
+ function = "sd0";
+ };
+ };
+
+ mmc2_default: mmc2_default {
+ pinmux {
+ groups = "nand0_d0_ceb3_mfp";
+ function = "sd2";
+ };
+ };
+};
+
+/* uSD */
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_default>;
+ no-sdio;
+ no-mmc;
+ no-1-8-v;
+ cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&sd_vcc>;
+ vqmmc-supply = <&sd_vcc>;
+};
+
+/* eMMC */
+&mmc2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_default>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ bus-width = <8>;
+ vmmc-supply = <&vcc_3v1>;
};
&timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 4/7] arm64: dts: actions: Add uSD and eMMC support for Bubblegum96
2019-09-16 15:45 ` [PATCH v4 4/7] arm64: dts: actions: Add uSD and eMMC support for Bubblegum96 Manivannan Sadhasivam
@ 2019-10-14 14:45 ` Manivannan Sadhasivam
0 siblings, 0 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-10-14 14:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk
On Mon, Sep 16, 2019 at 09:15:43PM +0530, Manivannan Sadhasivam wrote:
> Add uSD and eMMC support for Bubblegum96 board based on Actions Semi
> S900 SoC. SD0 is connected to uSD slot and SD2 is connected to eMMC.
> Since there is no PMIC support added yet, fixed regulator has been
> used as a regulator node.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for v5.5.
Thanks,
Mani
> ---
> .../boot/dts/actions/s900-bubblegum-96.dts | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
> index 732daaa6e9d3..59291e0ea1ee 100644
> --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
> +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
> @@ -12,6 +12,9 @@
> model = "Bubblegum-96";
>
> aliases {
> + mmc0 = &mmc0;
> + mmc1 = &mmc1;
> + mmc2 = &mmc2;
> serial5 = &uart5;
> };
>
> @@ -23,6 +26,24 @@
> device_type = "memory";
> reg = <0x0 0x0 0x0 0x80000000>;
> };
> +
> + /* Fixed regulator used in the absence of PMIC */
> + vcc_3v1: vcc-3v1 {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.1V";
> + regulator-min-microvolt = <3100000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-always-on;
> + };
> +
> + /* Fixed regulator used in the absence of PMIC */
> + sd_vcc: sd-vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.1V";
> + regulator-min-microvolt = <3100000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-always-on;
> + };
> };
>
> &i2c0 {
> @@ -241,6 +262,47 @@
> bias-pull-up;
> };
> };
> +
> + mmc0_default: mmc0_default {
> + pinmux {
> + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> + "sd0_cmd_mfp", "sd0_clk_mfp";
> + function = "sd0";
> + };
> + };
> +
> + mmc2_default: mmc2_default {
> + pinmux {
> + groups = "nand0_d0_ceb3_mfp";
> + function = "sd2";
> + };
> + };
> +};
> +
> +/* uSD */
> +&mmc0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_default>;
> + no-sdio;
> + no-mmc;
> + no-1-8-v;
> + cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + vmmc-supply = <&sd_vcc>;
> + vqmmc-supply = <&sd_vcc>;
> +};
> +
> +/* eMMC */
> +&mmc2 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_default>;
> + no-sdio;
> + no-sd;
> + non-removable;
> + bus-width = <8>;
> + vmmc-supply = <&vcc_3v1>;
> };
>
> &timer {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
` (3 preceding siblings ...)
2019-09-16 15:45 ` [PATCH v4 4/7] arm64: dts: actions: Add uSD and eMMC support for Bubblegum96 Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-10-03 10:01 ` Ulf Hansson
2019-09-16 15:45 ` [PATCH v4 6/7] MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding Manivannan Sadhasivam
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently
supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is
supported but it is untested. There is no SDIO support for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/mmc/host/Kconfig | 8 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/owl-mmc.c | 696 +++++++++++++++++++++++++++++++++++++
3 files changed, 705 insertions(+)
create mode 100644 drivers/mmc/host/owl-mmc.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 14d89a108edd..2c38e36953af 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -1006,3 +1006,11 @@ config MMC_SDHCI_AM654
If you have a controller with this interface, say Y or M here.
If unsure, say N.
+
+config MMC_OWL
+ tristate "Actions Semi Owl SD/MMC Host Controller support"
+ depends on HAS_DMA
+ depends on ARCH_ACTIONS || COMPILE_TEST
+ help
+ This selects support for the SD/MMC Host Controller on
+ Actions Semi Owl SoCs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 73578718f119..41a0b1728389 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835.o
+obj-$(CONFIG_MMC_OWL) += owl-mmc.o
obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
diff --git a/drivers/mmc/host/owl-mmc.c b/drivers/mmc/host/owl-mmc.c
new file mode 100644
index 000000000000..771e3d00f1bb
--- /dev/null
+++ b/drivers/mmc/host/owl-mmc.c
@@ -0,0 +1,696 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Actions Semi Owl SoCs SD/MMC driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ * TODO: SDIO support
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/slot-gpio.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+/*
+ * SDC registers
+ */
+#define OWL_REG_SD_EN 0x0000
+#define OWL_REG_SD_CTL 0x0004
+#define OWL_REG_SD_STATE 0x0008
+#define OWL_REG_SD_CMD 0x000c
+#define OWL_REG_SD_ARG 0x0010
+#define OWL_REG_SD_RSPBUF0 0x0014
+#define OWL_REG_SD_RSPBUF1 0x0018
+#define OWL_REG_SD_RSPBUF2 0x001c
+#define OWL_REG_SD_RSPBUF3 0x0020
+#define OWL_REG_SD_RSPBUF4 0x0024
+#define OWL_REG_SD_DAT 0x0028
+#define OWL_REG_SD_BLK_SIZE 0x002c
+#define OWL_REG_SD_BLK_NUM 0x0030
+#define OWL_REG_SD_BUF_SIZE 0x0034
+
+/* SD_EN Bits */
+#define OWL_SD_EN_RANE BIT(31)
+#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
+#define OWL_SD_EN_S18EN BIT(12)
+#define OWL_SD_EN_RESE BIT(10)
+#define OWL_SD_EN_DAT1_S BIT(9)
+#define OWL_SD_EN_CLK_S BIT(8)
+#define OWL_SD_ENABLE BIT(7)
+#define OWL_SD_EN_BSEL BIT(6)
+#define OWL_SD_EN_SDIOEN BIT(3)
+#define OWL_SD_EN_DDREN BIT(2)
+#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
+
+/* SD_CTL Bits */
+#define OWL_SD_CTL_TOUTEN BIT(31)
+#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
+#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
+#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
+#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
+#define OWL_SD_CTL_CMDLEN BIT(13)
+#define OWL_SD_CTL_SCC BIT(12)
+#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
+#define OWL_SD_CTL_TS BIT(7)
+#define OWL_SD_CTL_LBE BIT(6)
+#define OWL_SD_CTL_C7EN BIT(5)
+#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
+
+#define OWL_SD_DELAY_LOW_CLK 0x0f
+#define OWL_SD_DELAY_MID_CLK 0x0a
+#define OWL_SD_DELAY_HIGH_CLK 0x09
+#define OWL_SD_RDELAY_DDR50 0x0a
+#define OWL_SD_WDELAY_DDR50 0x08
+
+/* SD_STATE Bits */
+#define OWL_SD_STATE_DAT1BS BIT(18)
+#define OWL_SD_STATE_SDIOB_P BIT(17)
+#define OWL_SD_STATE_SDIOB_EN BIT(16)
+#define OWL_SD_STATE_TOUTE BIT(15)
+#define OWL_SD_STATE_BAEP BIT(14)
+#define OWL_SD_STATE_MEMRDY BIT(12)
+#define OWL_SD_STATE_CMDS BIT(11)
+#define OWL_SD_STATE_DAT1AS BIT(10)
+#define OWL_SD_STATE_SDIOA_P BIT(9)
+#define OWL_SD_STATE_SDIOA_EN BIT(8)
+#define OWL_SD_STATE_DAT0S BIT(7)
+#define OWL_SD_STATE_TEIE BIT(6)
+#define OWL_SD_STATE_TEI BIT(5)
+#define OWL_SD_STATE_CLNR BIT(4)
+#define OWL_SD_STATE_CLC BIT(3)
+#define OWL_SD_STATE_WC16ER BIT(2)
+#define OWL_SD_STATE_RC16ER BIT(1)
+#define OWL_SD_STATE_CRC7ER BIT(0)
+
+struct owl_mmc_host {
+ struct device *dev;
+ struct reset_control *reset;
+ void __iomem *base;
+ struct clk *clk;
+ struct completion sdc_complete;
+ spinlock_t lock;
+ int irq;
+ u32 clock;
+ bool ddr_50;
+
+ enum dma_data_direction dma_dir;
+ struct dma_chan *dma;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_slave_config dma_cfg;
+ struct completion dma_complete;
+
+ struct mmc_host *mmc;
+ struct mmc_request *mrq;
+ struct mmc_command *cmd;
+ struct mmc_data *data;
+};
+
+static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
+{
+ unsigned int regval;
+
+ regval = readl(reg);
+
+ if (state)
+ regval |= val;
+ else
+ regval &= ~val;
+
+ writel(regval, reg);
+}
+
+static irqreturn_t owl_irq_handler(int irq, void *devid)
+{
+ struct owl_mmc_host *owl_host = devid;
+ unsigned long flags;
+ u32 state;
+
+ spin_lock_irqsave(&owl_host->lock, flags);
+
+ state = readl(owl_host->base + OWL_REG_SD_STATE);
+ if (state & OWL_SD_STATE_TEI) {
+ state = readl(owl_host->base + OWL_REG_SD_STATE);
+ state |= OWL_SD_STATE_TEI;
+ writel(state, owl_host->base + OWL_REG_SD_STATE);
+ complete(&owl_host->sdc_complete);
+ }
+
+ spin_unlock_irqrestore(&owl_host->lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
+{
+ struct mmc_request *mrq = owl_host->mrq;
+ struct mmc_data *data = mrq->data;
+
+ /* Should never be NULL */
+ WARN_ON(!mrq);
+
+ owl_host->mrq = NULL;
+
+ if (data)
+ dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
+ owl_host->dma_dir);
+
+ /* Finally finish request */
+ mmc_request_done(owl_host->mmc, mrq);
+}
+
+static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
+ struct mmc_command *cmd,
+ struct mmc_data *data)
+{
+ u32 mode, state, resp[2];
+ u32 cmd_rsp_mask = 0;
+
+ init_completion(&owl_host->sdc_complete);
+
+ switch (mmc_resp_type(cmd)) {
+ case MMC_RSP_NONE:
+ mode = OWL_SD_CTL_TM(0);
+ break;
+
+ case MMC_RSP_R1:
+ if (data) {
+ if (data->flags & MMC_DATA_READ)
+ mode = OWL_SD_CTL_TM(4);
+ else
+ mode = OWL_SD_CTL_TM(5);
+ } else {
+ mode = OWL_SD_CTL_TM(1);
+ }
+ cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
+
+ break;
+
+ case MMC_RSP_R1B:
+ mode = OWL_SD_CTL_TM(3);
+ cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
+ break;
+
+ case MMC_RSP_R2:
+ mode = OWL_SD_CTL_TM(2);
+ cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
+ break;
+
+ case MMC_RSP_R3:
+ mode = OWL_SD_CTL_TM(1);
+ cmd_rsp_mask = OWL_SD_STATE_CLNR;
+ break;
+
+ default:
+ dev_warn(owl_host->dev, "Unknown MMC command\n");
+ cmd->error = -EINVAL;
+ return;
+ }
+
+ /* Keep current WDELAY and RDELAY */
+ mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
+
+ /* Start to send corresponding command type */
+ writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
+ writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
+
+ /* Set LBE to send clk at the end of last read block */
+ if (data) {
+ mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
+ } else {
+ mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
+ mode |= OWL_SD_CTL_TS;
+ }
+
+ owl_host->cmd = cmd;
+
+ /* Start transfer */
+ writel(mode, owl_host->base + OWL_REG_SD_CTL);
+
+ if (data)
+ return;
+
+ if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) {
+ dev_err(owl_host->dev, "CMD interrupt timeout\n");
+ cmd->error = -ETIMEDOUT;
+ return;
+ }
+
+ state = readl(owl_host->base + OWL_REG_SD_STATE);
+ if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
+ if (cmd_rsp_mask & state) {
+ if (state & OWL_SD_STATE_CLNR) {
+ dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
+ cmd->error = -EILSEQ;
+ return;
+ }
+
+ if (state & OWL_SD_STATE_CRC7ER) {
+ dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
+ cmd->error = -EILSEQ;
+ return;
+ }
+ }
+
+ if (mmc_resp_type(cmd) & MMC_RSP_136) {
+ cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
+ cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
+ cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
+ cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
+ } else {
+ resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
+ resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
+ cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
+ cmd->resp[1] = resp[1] >> 8;
+ }
+ }
+}
+
+static void owl_mmc_dma_complete(void *param)
+{
+ struct owl_mmc_host *owl_host = param;
+ struct mmc_data *data = owl_host->data;
+
+ if (data)
+ complete(&owl_host->dma_complete);
+}
+
+static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
+ struct mmc_data *data)
+{
+ u32 total;
+
+ owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
+ true);
+ writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
+ writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
+ total = data->blksz * data->blocks;
+
+ if (total < 512)
+ writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
+ else
+ writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
+
+ if (data->flags & MMC_DATA_WRITE) {
+ owl_host->dma_dir = DMA_TO_DEVICE;
+ owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
+ } else {
+ owl_host->dma_dir = DMA_FROM_DEVICE;
+ owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
+ }
+
+ dma_map_sg(owl_host->dma->device->dev, data->sg,
+ data->sg_len, owl_host->dma_dir);
+
+ dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
+ owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
+ data->sg_len,
+ owl_host->dma_cfg.direction,
+ DMA_PREP_INTERRUPT |
+ DMA_CTRL_ACK);
+ if (!owl_host->desc) {
+ dev_err(owl_host->dev, "Can't prepare slave sg\n");
+ return -EBUSY;
+ }
+
+ owl_host->data = data;
+
+ owl_host->desc->callback = owl_mmc_dma_complete;
+ owl_host->desc->callback_param = (void *)owl_host;
+ data->error = 0;
+
+ return 0;
+}
+
+static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct owl_mmc_host *owl_host = mmc_priv(mmc);
+ struct mmc_data *data = mrq->data;
+ int ret;
+
+ owl_host->mrq = mrq;
+ if (mrq->data) {
+ ret = owl_mmc_prepare_data(owl_host, data);
+ if (ret < 0) {
+ data->error = ret;
+ goto err_out;
+ }
+
+ init_completion(&owl_host->dma_complete);
+ dmaengine_submit(owl_host->desc);
+ dma_async_issue_pending(owl_host->dma);
+ }
+
+ owl_mmc_send_cmd(owl_host, mrq->cmd, data);
+
+ if (data) {
+ if (!wait_for_completion_timeout(&owl_host->sdc_complete,
+ 10 * HZ)) {
+ dev_err(owl_host->dev, "CMD interrupt timeout\n");
+ mrq->cmd->error = -ETIMEDOUT;
+ dmaengine_terminate_all(owl_host->dma);
+ goto err_out;
+ }
+
+ if (!wait_for_completion_timeout(&owl_host->dma_complete,
+ 5 * HZ)) {
+ dev_err(owl_host->dev, "DMA interrupt timeout\n");
+ mrq->cmd->error = -ETIMEDOUT;
+ dmaengine_terminate_all(owl_host->dma);
+ goto err_out;
+ }
+
+ if (data->stop)
+ owl_mmc_send_cmd(owl_host, data->stop, NULL);
+
+ data->bytes_xfered = data->blocks * data->blksz;
+ }
+
+err_out:
+ owl_mmc_finish_request(owl_host);
+}
+
+static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
+ unsigned int rate)
+{
+ unsigned long clk_rate;
+ int ret;
+ u32 reg;
+
+ reg = readl(owl_host->base + OWL_REG_SD_CTL);
+ reg &= ~OWL_SD_CTL_DELAY_MSK;
+
+ /* Set RDELAY and WDELAY based on the clock */
+ if (rate <= 1000000) {
+ writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
+ OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
+ owl_host->base + OWL_REG_SD_CTL);
+ } else if ((rate > 1000000) && (rate <= 26000000)) {
+ writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
+ OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
+ owl_host->base + OWL_REG_SD_CTL);
+ } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
+ writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
+ OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
+ owl_host->base + OWL_REG_SD_CTL);
+ /* DDR50 mode has special delay chain */
+ } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
+ writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
+ OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
+ owl_host->base + OWL_REG_SD_CTL);
+ } else {
+ dev_err(owl_host->dev, "SD clock rate not supported\n");
+ return -EINVAL;
+ }
+
+ clk_rate = clk_round_rate(owl_host->clk, rate << 1);
+ ret = clk_set_rate(owl_host->clk, clk_rate);
+
+ return ret;
+}
+
+static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
+{
+ if (!ios->clock)
+ return;
+
+ owl_host->clock = ios->clock;
+ owl_mmc_set_clk_rate(owl_host, ios->clock);
+}
+
+static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
+ struct mmc_ios *ios)
+{
+ u32 reg;
+
+ reg = readl(owl_host->base + OWL_REG_SD_EN);
+ reg &= ~0x03;
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_1:
+ break;
+ case MMC_BUS_WIDTH_4:
+ reg |= OWL_SD_EN_DATAWID(1);
+ break;
+ case MMC_BUS_WIDTH_8:
+ reg |= OWL_SD_EN_DATAWID(2);
+ break;
+ }
+
+ writel(reg, owl_host->base + OWL_REG_SD_EN);
+}
+
+static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
+{
+ reset_control_assert(owl_host->reset);
+ udelay(20);
+ reset_control_deassert(owl_host->reset);
+}
+
+static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
+{
+ u32 mode;
+
+ init_completion(&owl_host->sdc_complete);
+
+ /* Enable transfer end IRQ */
+ owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
+ OWL_SD_STATE_TEIE, true);
+
+ /* Send init clk */
+ mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
+ mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
+ writel(mode, owl_host->base + OWL_REG_SD_CTL);
+
+ if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
+ dev_err(owl_host->dev, "CMD interrupt timeout\n");
+ return;
+ }
+}
+
+static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct owl_mmc_host *owl_host = mmc_priv(mmc);
+
+ switch (ios->power_mode) {
+ case MMC_POWER_UP:
+ dev_dbg(owl_host->dev, "Powering card up\n");
+
+ /* Reset the SDC controller to clear all previous states */
+ owl_mmc_ctr_reset(owl_host);
+ clk_prepare_enable(owl_host->clk);
+ writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
+ owl_host->base + OWL_REG_SD_EN);
+
+ break;
+
+ case MMC_POWER_ON:
+ dev_dbg(owl_host->dev, "Powering card on\n");
+ owl_mmc_power_on(owl_host);
+
+ break;
+
+ case MMC_POWER_OFF:
+ dev_dbg(owl_host->dev, "Powering card off\n");
+ clk_disable_unprepare(owl_host->clk);
+
+ return;
+
+ default:
+ dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
+ break;
+ }
+
+ if (ios->clock != owl_host->clock)
+ owl_mmc_set_clk(owl_host, ios);
+
+ owl_mmc_set_bus_width(owl_host, ios);
+
+ /* Enable DDR mode if requested */
+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ owl_host->ddr_50 = 1;
+ owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
+ OWL_SD_EN_DDREN, true);
+ } else {
+ owl_host->ddr_50 = 0;
+ }
+}
+
+static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct owl_mmc_host *owl_host = mmc_priv(mmc);
+
+ /* It is enough to change the pad ctrl bit for voltage switch */
+ switch (ios->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
+ OWL_SD_EN_S18EN, false);
+ break;
+ case MMC_SIGNAL_VOLTAGE_180:
+ owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
+ OWL_SD_EN_S18EN, true);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+static const struct mmc_host_ops owl_mmc_ops = {
+ .request = owl_mmc_request,
+ .set_ios = owl_mmc_set_ios,
+ .get_ro = mmc_gpio_get_ro,
+ .get_cd = mmc_gpio_get_cd,
+ .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
+};
+
+static int owl_mmc_probe(struct platform_device *pdev)
+{
+ struct owl_mmc_host *owl_host;
+ struct mmc_host *mmc;
+ struct resource *res;
+ int ret;
+
+ mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
+ if (!mmc) {
+ dev_err(&pdev->dev, "mmc alloc host failed\n");
+ return -ENOMEM;
+ }
+ platform_set_drvdata(pdev, mmc);
+
+ owl_host = mmc_priv(mmc);
+ owl_host->dev = &pdev->dev;
+ owl_host->mmc = mmc;
+ spin_lock_init(&owl_host->lock);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ owl_host->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(owl_host->base)) {
+ dev_err(&pdev->dev, "Failed to remap registers\n");
+ ret = PTR_ERR(owl_host->base);
+ goto err_free_host;
+ }
+
+ owl_host->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(owl_host->clk)) {
+ dev_err(&pdev->dev, "No clock defined\n");
+ ret = PTR_ERR(owl_host->clk);
+ goto err_free_host;
+ }
+
+ owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(owl_host->reset)) {
+ dev_err(&pdev->dev, "Could not get reset control\n");
+ ret = PTR_ERR(owl_host->reset);
+ goto err_free_host;
+ }
+
+ mmc->ops = &owl_mmc_ops;
+ mmc->max_blk_count = 512;
+ mmc->max_blk_size = 512;
+ mmc->max_segs = 256;
+ mmc->max_seg_size = 262144;
+ mmc->max_req_size = 262144;
+ /* 100kHz ~ 52MHz */
+ mmc->f_min = 100000;
+ mmc->f_max = 52000000;
+ mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_4_BIT_DATA;
+ mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 |
+ MMC_VDD_165_195;
+
+ ret = mmc_of_parse(mmc);
+ if (ret)
+ goto err_free_host;
+
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+ owl_host->dma = dma_request_slave_channel(&pdev->dev, "mmc");
+ if (!owl_host->dma) {
+ dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
+ ret = -ENXIO;
+ goto err_free_host;
+ }
+
+ dev_info(&pdev->dev, "Using %s for DMA transfers\n",
+ dma_chan_name(owl_host->dma));
+
+ owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
+ owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
+ owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ owl_host->dma_cfg.device_fc = false;
+
+ owl_host->irq = platform_get_irq(pdev, 0);
+ if (owl_host->irq < 0) {
+ ret = -EINVAL;
+ goto err_free_host;
+ }
+
+ ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
+ 0, dev_name(&pdev->dev), owl_host);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to request irq %d\n",
+ owl_host->irq);
+ goto err_free_host;
+ }
+
+ ret = mmc_add_host(mmc);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add host\n");
+ goto err_free_host;
+ }
+
+ dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
+
+ return 0;
+
+err_free_host:
+ mmc_free_host(mmc);
+
+ return ret;
+}
+
+static int owl_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct owl_mmc_host *owl_host = mmc_priv(mmc);
+
+ mmc_remove_host(mmc);
+ disable_irq(owl_host->irq);
+ mmc_free_host(mmc);
+
+ return 0;
+}
+
+static const struct of_device_id owl_mmc_of_match[] = {
+ {.compatible = "actions,owl-mmc",},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
+
+static struct platform_driver owl_mmc_driver = {
+ .driver = {
+ .name = "owl_mmc",
+ .of_match_table = of_match_ptr(owl_mmc_of_match),
+ },
+ .probe = owl_mmc_probe,
+ .remove = owl_mmc_remove,
+};
+module_platform_driver(owl_mmc_driver);
+
+MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
+MODULE_AUTHOR("Actions Semi");
+MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver
2019-09-16 15:45 ` [PATCH v4 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver Manivannan Sadhasivam
@ 2019-10-03 10:01 ` Ulf Hansson
0 siblings, 0 replies; 21+ messages in thread
From: Ulf Hansson @ 2019-10-03 10:01 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Andreas Färber, Rob Herring, Stephen Boyd, Linux ARM,
linux-mmc, Linux Kernel Mailing List, DTML, thomas.liau,
linux-actions, Linus Walleij, linux-clk
On Mon, 16 Sep 2019 at 17:46, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently
> supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is
> supported but it is untested. There is no SDIO support for now.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/Kconfig | 8 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/owl-mmc.c | 696 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 705 insertions(+)
> create mode 100644 drivers/mmc/host/owl-mmc.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 14d89a108edd..2c38e36953af 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -1006,3 +1006,11 @@ config MMC_SDHCI_AM654
> If you have a controller with this interface, say Y or M here.
>
> If unsure, say N.
> +
> +config MMC_OWL
> + tristate "Actions Semi Owl SD/MMC Host Controller support"
> + depends on HAS_DMA
> + depends on ARCH_ACTIONS || COMPILE_TEST
> + help
> + This selects support for the SD/MMC Host Controller on
> + Actions Semi Owl SoCs.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 73578718f119..41a0b1728389 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -73,6 +73,7 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
> obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
> obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o
> obj-$(CONFIG_MMC_BCM2835) += bcm2835.o
> +obj-$(CONFIG_MMC_OWL) += owl-mmc.o
>
> obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
> obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
> diff --git a/drivers/mmc/host/owl-mmc.c b/drivers/mmc/host/owl-mmc.c
> new file mode 100644
> index 000000000000..771e3d00f1bb
> --- /dev/null
> +++ b/drivers/mmc/host/owl-mmc.c
> @@ -0,0 +1,696 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Actions Semi Owl SoCs SD/MMC driver
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> + *
> + * TODO: SDIO support
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-direction.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/interrupt.h>
> +#include <linux/mmc/host.h>
> +#include <linux/mmc/slot-gpio.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/reset.h>
> +#include <linux/spinlock.h>
> +
> +/*
> + * SDC registers
> + */
> +#define OWL_REG_SD_EN 0x0000
> +#define OWL_REG_SD_CTL 0x0004
> +#define OWL_REG_SD_STATE 0x0008
> +#define OWL_REG_SD_CMD 0x000c
> +#define OWL_REG_SD_ARG 0x0010
> +#define OWL_REG_SD_RSPBUF0 0x0014
> +#define OWL_REG_SD_RSPBUF1 0x0018
> +#define OWL_REG_SD_RSPBUF2 0x001c
> +#define OWL_REG_SD_RSPBUF3 0x0020
> +#define OWL_REG_SD_RSPBUF4 0x0024
> +#define OWL_REG_SD_DAT 0x0028
> +#define OWL_REG_SD_BLK_SIZE 0x002c
> +#define OWL_REG_SD_BLK_NUM 0x0030
> +#define OWL_REG_SD_BUF_SIZE 0x0034
> +
> +/* SD_EN Bits */
> +#define OWL_SD_EN_RANE BIT(31)
> +#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
> +#define OWL_SD_EN_S18EN BIT(12)
> +#define OWL_SD_EN_RESE BIT(10)
> +#define OWL_SD_EN_DAT1_S BIT(9)
> +#define OWL_SD_EN_CLK_S BIT(8)
> +#define OWL_SD_ENABLE BIT(7)
> +#define OWL_SD_EN_BSEL BIT(6)
> +#define OWL_SD_EN_SDIOEN BIT(3)
> +#define OWL_SD_EN_DDREN BIT(2)
> +#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
> +
> +/* SD_CTL Bits */
> +#define OWL_SD_CTL_TOUTEN BIT(31)
> +#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
> +#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
> +#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
> +#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
> +#define OWL_SD_CTL_CMDLEN BIT(13)
> +#define OWL_SD_CTL_SCC BIT(12)
> +#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
> +#define OWL_SD_CTL_TS BIT(7)
> +#define OWL_SD_CTL_LBE BIT(6)
> +#define OWL_SD_CTL_C7EN BIT(5)
> +#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
> +
> +#define OWL_SD_DELAY_LOW_CLK 0x0f
> +#define OWL_SD_DELAY_MID_CLK 0x0a
> +#define OWL_SD_DELAY_HIGH_CLK 0x09
> +#define OWL_SD_RDELAY_DDR50 0x0a
> +#define OWL_SD_WDELAY_DDR50 0x08
> +
> +/* SD_STATE Bits */
> +#define OWL_SD_STATE_DAT1BS BIT(18)
> +#define OWL_SD_STATE_SDIOB_P BIT(17)
> +#define OWL_SD_STATE_SDIOB_EN BIT(16)
> +#define OWL_SD_STATE_TOUTE BIT(15)
> +#define OWL_SD_STATE_BAEP BIT(14)
> +#define OWL_SD_STATE_MEMRDY BIT(12)
> +#define OWL_SD_STATE_CMDS BIT(11)
> +#define OWL_SD_STATE_DAT1AS BIT(10)
> +#define OWL_SD_STATE_SDIOA_P BIT(9)
> +#define OWL_SD_STATE_SDIOA_EN BIT(8)
> +#define OWL_SD_STATE_DAT0S BIT(7)
> +#define OWL_SD_STATE_TEIE BIT(6)
> +#define OWL_SD_STATE_TEI BIT(5)
> +#define OWL_SD_STATE_CLNR BIT(4)
> +#define OWL_SD_STATE_CLC BIT(3)
> +#define OWL_SD_STATE_WC16ER BIT(2)
> +#define OWL_SD_STATE_RC16ER BIT(1)
> +#define OWL_SD_STATE_CRC7ER BIT(0)
> +
> +struct owl_mmc_host {
> + struct device *dev;
> + struct reset_control *reset;
> + void __iomem *base;
> + struct clk *clk;
> + struct completion sdc_complete;
> + spinlock_t lock;
> + int irq;
> + u32 clock;
> + bool ddr_50;
> +
> + enum dma_data_direction dma_dir;
> + struct dma_chan *dma;
> + struct dma_async_tx_descriptor *desc;
> + struct dma_slave_config dma_cfg;
> + struct completion dma_complete;
> +
> + struct mmc_host *mmc;
> + struct mmc_request *mrq;
> + struct mmc_command *cmd;
> + struct mmc_data *data;
> +};
> +
> +static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
> +{
> + unsigned int regval;
> +
> + regval = readl(reg);
> +
> + if (state)
> + regval |= val;
> + else
> + regval &= ~val;
> +
> + writel(regval, reg);
> +}
> +
> +static irqreturn_t owl_irq_handler(int irq, void *devid)
> +{
> + struct owl_mmc_host *owl_host = devid;
> + unsigned long flags;
> + u32 state;
> +
> + spin_lock_irqsave(&owl_host->lock, flags);
> +
> + state = readl(owl_host->base + OWL_REG_SD_STATE);
> + if (state & OWL_SD_STATE_TEI) {
> + state = readl(owl_host->base + OWL_REG_SD_STATE);
> + state |= OWL_SD_STATE_TEI;
> + writel(state, owl_host->base + OWL_REG_SD_STATE);
> + complete(&owl_host->sdc_complete);
> + }
> +
> + spin_unlock_irqrestore(&owl_host->lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
> +{
> + struct mmc_request *mrq = owl_host->mrq;
> + struct mmc_data *data = mrq->data;
> +
> + /* Should never be NULL */
> + WARN_ON(!mrq);
> +
> + owl_host->mrq = NULL;
> +
> + if (data)
> + dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
> + owl_host->dma_dir);
> +
> + /* Finally finish request */
> + mmc_request_done(owl_host->mmc, mrq);
> +}
> +
> +static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
> + struct mmc_command *cmd,
> + struct mmc_data *data)
> +{
> + u32 mode, state, resp[2];
> + u32 cmd_rsp_mask = 0;
> +
> + init_completion(&owl_host->sdc_complete);
> +
> + switch (mmc_resp_type(cmd)) {
> + case MMC_RSP_NONE:
> + mode = OWL_SD_CTL_TM(0);
> + break;
> +
> + case MMC_RSP_R1:
> + if (data) {
> + if (data->flags & MMC_DATA_READ)
> + mode = OWL_SD_CTL_TM(4);
> + else
> + mode = OWL_SD_CTL_TM(5);
> + } else {
> + mode = OWL_SD_CTL_TM(1);
> + }
> + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
> +
> + break;
> +
> + case MMC_RSP_R1B:
> + mode = OWL_SD_CTL_TM(3);
> + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
> + break;
> +
> + case MMC_RSP_R2:
> + mode = OWL_SD_CTL_TM(2);
> + cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
> + break;
> +
> + case MMC_RSP_R3:
> + mode = OWL_SD_CTL_TM(1);
> + cmd_rsp_mask = OWL_SD_STATE_CLNR;
> + break;
> +
> + default:
> + dev_warn(owl_host->dev, "Unknown MMC command\n");
> + cmd->error = -EINVAL;
> + return;
> + }
> +
> + /* Keep current WDELAY and RDELAY */
> + mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
> +
> + /* Start to send corresponding command type */
> + writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
> + writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
> +
> + /* Set LBE to send clk at the end of last read block */
> + if (data) {
> + mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
> + } else {
> + mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
> + mode |= OWL_SD_CTL_TS;
> + }
> +
> + owl_host->cmd = cmd;
> +
> + /* Start transfer */
> + writel(mode, owl_host->base + OWL_REG_SD_CTL);
> +
> + if (data)
> + return;
> +
> + if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) {
> + dev_err(owl_host->dev, "CMD interrupt timeout\n");
> + cmd->error = -ETIMEDOUT;
> + return;
> + }
> +
> + state = readl(owl_host->base + OWL_REG_SD_STATE);
> + if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
> + if (cmd_rsp_mask & state) {
> + if (state & OWL_SD_STATE_CLNR) {
> + dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
> + cmd->error = -EILSEQ;
> + return;
> + }
> +
> + if (state & OWL_SD_STATE_CRC7ER) {
> + dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
> + cmd->error = -EILSEQ;
> + return;
> + }
> + }
> +
> + if (mmc_resp_type(cmd) & MMC_RSP_136) {
> + cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
> + cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
> + cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
> + cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
> + } else {
> + resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
> + resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
> + cmd->resp[0] = resp[1] << 24 | resp[0] >> 8;
> + cmd->resp[1] = resp[1] >> 8;
> + }
> + }
> +}
> +
> +static void owl_mmc_dma_complete(void *param)
> +{
> + struct owl_mmc_host *owl_host = param;
> + struct mmc_data *data = owl_host->data;
> +
> + if (data)
> + complete(&owl_host->dma_complete);
> +}
> +
> +static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
> + struct mmc_data *data)
> +{
> + u32 total;
> +
> + owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
> + true);
> + writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
> + writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
> + total = data->blksz * data->blocks;
> +
> + if (total < 512)
> + writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
> + else
> + writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
> +
> + if (data->flags & MMC_DATA_WRITE) {
> + owl_host->dma_dir = DMA_TO_DEVICE;
> + owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
> + } else {
> + owl_host->dma_dir = DMA_FROM_DEVICE;
> + owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
> + }
> +
> + dma_map_sg(owl_host->dma->device->dev, data->sg,
> + data->sg_len, owl_host->dma_dir);
> +
> + dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
> + owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
> + data->sg_len,
> + owl_host->dma_cfg.direction,
> + DMA_PREP_INTERRUPT |
> + DMA_CTRL_ACK);
> + if (!owl_host->desc) {
> + dev_err(owl_host->dev, "Can't prepare slave sg\n");
> + return -EBUSY;
> + }
> +
> + owl_host->data = data;
> +
> + owl_host->desc->callback = owl_mmc_dma_complete;
> + owl_host->desc->callback_param = (void *)owl_host;
> + data->error = 0;
> +
> + return 0;
> +}
> +
> +static void owl_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
> +{
> + struct owl_mmc_host *owl_host = mmc_priv(mmc);
> + struct mmc_data *data = mrq->data;
> + int ret;
> +
> + owl_host->mrq = mrq;
> + if (mrq->data) {
> + ret = owl_mmc_prepare_data(owl_host, data);
> + if (ret < 0) {
> + data->error = ret;
> + goto err_out;
> + }
> +
> + init_completion(&owl_host->dma_complete);
> + dmaengine_submit(owl_host->desc);
> + dma_async_issue_pending(owl_host->dma);
> + }
> +
> + owl_mmc_send_cmd(owl_host, mrq->cmd, data);
> +
> + if (data) {
> + if (!wait_for_completion_timeout(&owl_host->sdc_complete,
> + 10 * HZ)) {
> + dev_err(owl_host->dev, "CMD interrupt timeout\n");
> + mrq->cmd->error = -ETIMEDOUT;
> + dmaengine_terminate_all(owl_host->dma);
> + goto err_out;
> + }
> +
> + if (!wait_for_completion_timeout(&owl_host->dma_complete,
> + 5 * HZ)) {
> + dev_err(owl_host->dev, "DMA interrupt timeout\n");
> + mrq->cmd->error = -ETIMEDOUT;
> + dmaengine_terminate_all(owl_host->dma);
> + goto err_out;
> + }
> +
> + if (data->stop)
> + owl_mmc_send_cmd(owl_host, data->stop, NULL);
> +
> + data->bytes_xfered = data->blocks * data->blksz;
> + }
> +
> +err_out:
> + owl_mmc_finish_request(owl_host);
> +}
> +
> +static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
> + unsigned int rate)
> +{
> + unsigned long clk_rate;
> + int ret;
> + u32 reg;
> +
> + reg = readl(owl_host->base + OWL_REG_SD_CTL);
> + reg &= ~OWL_SD_CTL_DELAY_MSK;
> +
> + /* Set RDELAY and WDELAY based on the clock */
> + if (rate <= 1000000) {
> + writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
> + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
> + owl_host->base + OWL_REG_SD_CTL);
> + } else if ((rate > 1000000) && (rate <= 26000000)) {
> + writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
> + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
> + owl_host->base + OWL_REG_SD_CTL);
> + } else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
> + writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
> + OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
> + owl_host->base + OWL_REG_SD_CTL);
> + /* DDR50 mode has special delay chain */
> + } else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
> + writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
> + OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
> + owl_host->base + OWL_REG_SD_CTL);
> + } else {
> + dev_err(owl_host->dev, "SD clock rate not supported\n");
> + return -EINVAL;
> + }
> +
> + clk_rate = clk_round_rate(owl_host->clk, rate << 1);
> + ret = clk_set_rate(owl_host->clk, clk_rate);
> +
> + return ret;
> +}
> +
> +static void owl_mmc_set_clk(struct owl_mmc_host *owl_host, struct mmc_ios *ios)
> +{
> + if (!ios->clock)
> + return;
> +
> + owl_host->clock = ios->clock;
> + owl_mmc_set_clk_rate(owl_host, ios->clock);
> +}
> +
> +static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
> + struct mmc_ios *ios)
> +{
> + u32 reg;
> +
> + reg = readl(owl_host->base + OWL_REG_SD_EN);
> + reg &= ~0x03;
> + switch (ios->bus_width) {
> + case MMC_BUS_WIDTH_1:
> + break;
> + case MMC_BUS_WIDTH_4:
> + reg |= OWL_SD_EN_DATAWID(1);
> + break;
> + case MMC_BUS_WIDTH_8:
> + reg |= OWL_SD_EN_DATAWID(2);
> + break;
> + }
> +
> + writel(reg, owl_host->base + OWL_REG_SD_EN);
> +}
> +
> +static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
> +{
> + reset_control_assert(owl_host->reset);
> + udelay(20);
> + reset_control_deassert(owl_host->reset);
> +}
> +
> +static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
> +{
> + u32 mode;
> +
> + init_completion(&owl_host->sdc_complete);
> +
> + /* Enable transfer end IRQ */
> + owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
> + OWL_SD_STATE_TEIE, true);
> +
> + /* Send init clk */
> + mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
> + mode |= OWL_SD_CTL_TS | OWL_SD_CTL_TCN(5) | OWL_SD_CTL_TM(8);
> + writel(mode, owl_host->base + OWL_REG_SD_CTL);
> +
> + if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
> + dev_err(owl_host->dev, "CMD interrupt timeout\n");
> + return;
> + }
> +}
> +
> +static void owl_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> + struct owl_mmc_host *owl_host = mmc_priv(mmc);
> +
> + switch (ios->power_mode) {
> + case MMC_POWER_UP:
> + dev_dbg(owl_host->dev, "Powering card up\n");
> +
> + /* Reset the SDC controller to clear all previous states */
> + owl_mmc_ctr_reset(owl_host);
> + clk_prepare_enable(owl_host->clk);
> + writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
> + owl_host->base + OWL_REG_SD_EN);
> +
> + break;
> +
> + case MMC_POWER_ON:
> + dev_dbg(owl_host->dev, "Powering card on\n");
> + owl_mmc_power_on(owl_host);
> +
> + break;
> +
> + case MMC_POWER_OFF:
> + dev_dbg(owl_host->dev, "Powering card off\n");
> + clk_disable_unprepare(owl_host->clk);
> +
> + return;
> +
> + default:
> + dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
> + break;
> + }
> +
> + if (ios->clock != owl_host->clock)
> + owl_mmc_set_clk(owl_host, ios);
> +
> + owl_mmc_set_bus_width(owl_host, ios);
> +
> + /* Enable DDR mode if requested */
> + if (ios->timing == MMC_TIMING_UHS_DDR50) {
> + owl_host->ddr_50 = 1;
> + owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
> + OWL_SD_EN_DDREN, true);
> + } else {
> + owl_host->ddr_50 = 0;
> + }
> +}
> +
> +static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
> + struct mmc_ios *ios)
> +{
> + struct owl_mmc_host *owl_host = mmc_priv(mmc);
> +
> + /* It is enough to change the pad ctrl bit for voltage switch */
> + switch (ios->signal_voltage) {
> + case MMC_SIGNAL_VOLTAGE_330:
> + owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
> + OWL_SD_EN_S18EN, false);
> + break;
> + case MMC_SIGNAL_VOLTAGE_180:
> + owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
> + OWL_SD_EN_S18EN, true);
> + break;
> + default:
> + return -ENOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static const struct mmc_host_ops owl_mmc_ops = {
> + .request = owl_mmc_request,
> + .set_ios = owl_mmc_set_ios,
> + .get_ro = mmc_gpio_get_ro,
> + .get_cd = mmc_gpio_get_cd,
> + .start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
> +};
> +
> +static int owl_mmc_probe(struct platform_device *pdev)
> +{
> + struct owl_mmc_host *owl_host;
> + struct mmc_host *mmc;
> + struct resource *res;
> + int ret;
> +
> + mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
> + if (!mmc) {
> + dev_err(&pdev->dev, "mmc alloc host failed\n");
> + return -ENOMEM;
> + }
> + platform_set_drvdata(pdev, mmc);
> +
> + owl_host = mmc_priv(mmc);
> + owl_host->dev = &pdev->dev;
> + owl_host->mmc = mmc;
> + spin_lock_init(&owl_host->lock);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + owl_host->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(owl_host->base)) {
> + dev_err(&pdev->dev, "Failed to remap registers\n");
> + ret = PTR_ERR(owl_host->base);
> + goto err_free_host;
> + }
> +
> + owl_host->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(owl_host->clk)) {
> + dev_err(&pdev->dev, "No clock defined\n");
> + ret = PTR_ERR(owl_host->clk);
> + goto err_free_host;
> + }
> +
> + owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(owl_host->reset)) {
> + dev_err(&pdev->dev, "Could not get reset control\n");
> + ret = PTR_ERR(owl_host->reset);
> + goto err_free_host;
> + }
> +
> + mmc->ops = &owl_mmc_ops;
> + mmc->max_blk_count = 512;
> + mmc->max_blk_size = 512;
> + mmc->max_segs = 256;
> + mmc->max_seg_size = 262144;
> + mmc->max_req_size = 262144;
> + /* 100kHz ~ 52MHz */
> + mmc->f_min = 100000;
> + mmc->f_max = 52000000;
> + mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> + MMC_CAP_4_BIT_DATA;
> + mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC | MMC_CAP2_NO_SDIO);
> + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 |
> + MMC_VDD_165_195;
> +
> + ret = mmc_of_parse(mmc);
> + if (ret)
> + goto err_free_host;
> +
> + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
> + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
> + owl_host->dma = dma_request_slave_channel(&pdev->dev, "mmc");
> + if (!owl_host->dma) {
> + dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
> + ret = -ENXIO;
> + goto err_free_host;
> + }
> +
> + dev_info(&pdev->dev, "Using %s for DMA transfers\n",
> + dma_chan_name(owl_host->dma));
> +
> + owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
> + owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
> + owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> + owl_host->dma_cfg.device_fc = false;
> +
> + owl_host->irq = platform_get_irq(pdev, 0);
> + if (owl_host->irq < 0) {
> + ret = -EINVAL;
> + goto err_free_host;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
> + 0, dev_name(&pdev->dev), owl_host);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to request irq %d\n",
> + owl_host->irq);
> + goto err_free_host;
> + }
> +
> + ret = mmc_add_host(mmc);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to add host\n");
> + goto err_free_host;
> + }
> +
> + dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
> +
> + return 0;
> +
> +err_free_host:
> + mmc_free_host(mmc);
> +
> + return ret;
> +}
> +
> +static int owl_mmc_remove(struct platform_device *pdev)
> +{
> + struct mmc_host *mmc = platform_get_drvdata(pdev);
> + struct owl_mmc_host *owl_host = mmc_priv(mmc);
> +
> + mmc_remove_host(mmc);
> + disable_irq(owl_host->irq);
> + mmc_free_host(mmc);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id owl_mmc_of_match[] = {
> + {.compatible = "actions,owl-mmc",},
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
> +
> +static struct platform_driver owl_mmc_driver = {
> + .driver = {
> + .name = "owl_mmc",
> + .of_match_table = of_match_ptr(owl_mmc_of_match),
> + },
> + .probe = owl_mmc_probe,
> + .remove = owl_mmc_remove,
> +};
> +module_platform_driver(owl_mmc_driver);
> +
> +MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
> +MODULE_AUTHOR("Actions Semi");
> +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> +MODULE_LICENSE("GPL");
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 6/7] MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
` (4 preceding siblings ...)
2019-09-16 15:45 ` [PATCH v4 5/7] mmc: Add Actions Semi Owl SoCs SD/MMC driver Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-10-03 10:01 ` Ulf Hansson
2019-09-16 15:45 ` [PATCH v4 7/7] arm64: configs: Enable Actions Semi platform in defconfig Manivannan Sadhasivam
2019-10-03 10:01 ` [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Ulf Hansson
7 siblings, 1 reply; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Add MAINTAINERS entry for Actions Semi SD/MMC driver with its binding.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c31e6492b601..d13138330b97 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1375,6 +1375,7 @@ F: drivers/clk/actions/
F: drivers/clocksource/timer-owl*
F: drivers/dma/owl-dma.c
F: drivers/i2c/busses/i2c-owl.c
+F: drivers/mmc/host/owl-mmc.c
F: drivers/pinctrl/actions/*
F: drivers/soc/actions/
F: include/dt-bindings/power/owl-*
@@ -1383,6 +1384,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
F: Documentation/devicetree/bindings/dma/owl-dma.txt
F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
+F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 6/7] MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding
2019-09-16 15:45 ` [PATCH v4 6/7] MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding Manivannan Sadhasivam
@ 2019-10-03 10:01 ` Ulf Hansson
0 siblings, 0 replies; 21+ messages in thread
From: Ulf Hansson @ 2019-10-03 10:01 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Andreas Färber, Rob Herring, Stephen Boyd, Linux ARM,
linux-mmc, Linux Kernel Mailing List, DTML, thomas.liau,
linux-actions, Linus Walleij, linux-clk
On Mon, 16 Sep 2019 at 17:46, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Add MAINTAINERS entry for Actions Semi SD/MMC driver with its binding.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for next, thanks!
Kind regards
Uffe
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c31e6492b601..d13138330b97 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1375,6 +1375,7 @@ F: drivers/clk/actions/
> F: drivers/clocksource/timer-owl*
> F: drivers/dma/owl-dma.c
> F: drivers/i2c/busses/i2c-owl.c
> +F: drivers/mmc/host/owl-mmc.c
> F: drivers/pinctrl/actions/*
> F: drivers/soc/actions/
> F: include/dt-bindings/power/owl-*
> @@ -1383,6 +1384,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml
> F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
> F: Documentation/devicetree/bindings/dma/owl-dma.txt
> F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
> +F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
> F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
> F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v4 7/7] arm64: configs: Enable Actions Semi platform in defconfig
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
` (5 preceding siblings ...)
2019-09-16 15:45 ` [PATCH v4 6/7] MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding Manivannan Sadhasivam
@ 2019-09-16 15:45 ` Manivannan Sadhasivam
2019-10-14 14:46 ` Manivannan Sadhasivam
2019-10-03 10:01 ` [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Ulf Hansson
7 siblings, 1 reply; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-09-16 15:45 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk,
Manivannan Sadhasivam
Since the Actions Semi platform can now boot a distro, enable it in
ARM64 defconfig.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0e58ef02880c..8e27777d6687 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -29,6 +29,7 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
+CONFIG_ARCH_ACTIONS=y
CONFIG_ARCH_AGILEX=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v4 7/7] arm64: configs: Enable Actions Semi platform in defconfig
2019-09-16 15:45 ` [PATCH v4 7/7] arm64: configs: Enable Actions Semi platform in defconfig Manivannan Sadhasivam
@ 2019-10-14 14:46 ` Manivannan Sadhasivam
0 siblings, 0 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-10-14 14:46 UTC (permalink / raw)
To: ulf.hansson, afaerber, robh+dt, sboyd
Cc: linux-arm-kernel, linux-mmc, linux-kernel, devicetree,
thomas.liau, linux-actions, linus.walleij, linux-clk
On Mon, Sep 16, 2019 at 09:15:46PM +0530, Manivannan Sadhasivam wrote:
> Since the Actions Semi platform can now boot a distro, enable it in
> ARM64 defconfig.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied for v5.5.
Thanks,
Mani
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 0e58ef02880c..8e27777d6687 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -29,6 +29,7 @@ CONFIG_BLK_DEV_INITRD=y
> CONFIG_KALLSYMS_ALL=y
> # CONFIG_COMPAT_BRK is not set
> CONFIG_PROFILING=y
> +CONFIG_ARCH_ACTIONS=y
> CONFIG_ARCH_AGILEX=y
> CONFIG_ARCH_SUNXI=y
> CONFIG_ARCH_ALPINE=y
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC
2019-09-16 15:45 [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Manivannan Sadhasivam
` (6 preceding siblings ...)
2019-09-16 15:45 ` [PATCH v4 7/7] arm64: configs: Enable Actions Semi platform in defconfig Manivannan Sadhasivam
@ 2019-10-03 10:01 ` Ulf Hansson
2019-10-03 16:17 ` Manivannan Sadhasivam
7 siblings, 1 reply; 21+ messages in thread
From: Ulf Hansson @ 2019-10-03 10:01 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Andreas Färber, Rob Herring, Stephen Boyd, Linux ARM,
linux-mmc, Linux Kernel Mailing List, DTML, thomas.liau,
linux-actions, Linus Walleij, linux-clk
On Mon, 16 Sep 2019 at 17:46, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> Hello,
>
> This patchset adds SD/MMC driver for Actions Semi S900 SoC from Owl
> family SoCs. There are 4 SD/MMC controller present in this SoC but
> only 2 are enabled currently for Bubblegum96 board to access uSD and
> onboard eMMC. SDIO support for this driver is not currently implemented.
>
> Note: Currently, driver uses 2 completion mechanisms for maintaining
> the coherency between SDC and DMA interrupts and I know that it is not
> efficient. Hence, I'd like to hear any suggestions for reimplementing
> the logic if anyone has.
>
> With this driver, this patchset also fixes one clk driver issue and enables
> the Actions Semi platform in ARM64 defconfig.
>
> Thanks,
> Mani
>
> Changes in v4:
>
> * Incorporated review comments from Rob on dt binding
>
> Changes in v3:
>
> * Incorporated a review comment from Andreas on board dts patch
> * Modified the MAINTAINERS entry for devicetree YAML binding
>
> Changes in v2:
>
> * Converted the devicetree bindings to YAML
> * Misc changes to bubblegum devicetree as per the review from Andreas
> * Dropped the read/write wrappers and renamed all functions to use owl-
> prefix as per the review from Ulf
> * Renamed clk_val_best to owl_clk_val_best and added Reviewed-by tag
> from Stephen
>
> Manivannan Sadhasivam (7):
> clk: actions: Fix factor clk struct member access
> dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
> arm64: dts: actions: Add MMC controller support for S900
> arm64: dts: actions: Add uSD and eMMC support for Bubblegum96
> mmc: Add Actions Semi Owl SoCs SD/MMC driver
> MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding
> arm64: configs: Enable Actions Semi platform in defconfig
>
> .../devicetree/bindings/mmc/owl-mmc.yaml | 59 ++
> MAINTAINERS | 2 +
> .../boot/dts/actions/s900-bubblegum-96.dts | 62 ++
> arch/arm64/boot/dts/actions/s900.dtsi | 45 ++
> arch/arm64/configs/defconfig | 1 +
> drivers/clk/actions/owl-factor.c | 7 +-
> drivers/mmc/host/Kconfig | 8 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/owl-mmc.c | 696 ++++++++++++++++++
> 9 files changed, 877 insertions(+), 4 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> create mode 100644 drivers/mmc/host/owl-mmc.c
>
> --
> 2.17.1
>
I have picked up the mmc patches for next and as Stephen picked the
clock patch, the rest are now for arm-soc, I guess!?
Kind regards
Uffe
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC
2019-10-03 10:01 ` [PATCH v4 0/7] Add SD/MMC driver for Actions Semi S900 SoC Ulf Hansson
@ 2019-10-03 16:17 ` Manivannan Sadhasivam
0 siblings, 0 replies; 21+ messages in thread
From: Manivannan Sadhasivam @ 2019-10-03 16:17 UTC (permalink / raw)
To: Ulf Hansson
Cc: Andreas Färber, Rob Herring, Stephen Boyd, Linux ARM,
linux-mmc, Linux Kernel Mailing List, DTML, thomas.liau,
linux-actions, Linus Walleij, linux-clk
Hi Ulf,
On Thu, Oct 03, 2019 at 12:01:18PM +0200, Ulf Hansson wrote:
> On Mon, 16 Sep 2019 at 17:46, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > Hello,
> >
> > This patchset adds SD/MMC driver for Actions Semi S900 SoC from Owl
> > family SoCs. There are 4 SD/MMC controller present in this SoC but
> > only 2 are enabled currently for Bubblegum96 board to access uSD and
> > onboard eMMC. SDIO support for this driver is not currently implemented.
> >
> > Note: Currently, driver uses 2 completion mechanisms for maintaining
> > the coherency between SDC and DMA interrupts and I know that it is not
> > efficient. Hence, I'd like to hear any suggestions for reimplementing
> > the logic if anyone has.
> >
> > With this driver, this patchset also fixes one clk driver issue and enables
> > the Actions Semi platform in ARM64 defconfig.
> >
> > Thanks,
> > Mani
> >
> > Changes in v4:
> >
> > * Incorporated review comments from Rob on dt binding
> >
> > Changes in v3:
> >
> > * Incorporated a review comment from Andreas on board dts patch
> > * Modified the MAINTAINERS entry for devicetree YAML binding
> >
> > Changes in v2:
> >
> > * Converted the devicetree bindings to YAML
> > * Misc changes to bubblegum devicetree as per the review from Andreas
> > * Dropped the read/write wrappers and renamed all functions to use owl-
> > prefix as per the review from Ulf
> > * Renamed clk_val_best to owl_clk_val_best and added Reviewed-by tag
> > from Stephen
> >
> > Manivannan Sadhasivam (7):
> > clk: actions: Fix factor clk struct member access
> > dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
> > arm64: dts: actions: Add MMC controller support for S900
> > arm64: dts: actions: Add uSD and eMMC support for Bubblegum96
> > mmc: Add Actions Semi Owl SoCs SD/MMC driver
> > MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding
> > arm64: configs: Enable Actions Semi platform in defconfig
> >
> > .../devicetree/bindings/mmc/owl-mmc.yaml | 59 ++
> > MAINTAINERS | 2 +
> > .../boot/dts/actions/s900-bubblegum-96.dts | 62 ++
> > arch/arm64/boot/dts/actions/s900.dtsi | 45 ++
> > arch/arm64/configs/defconfig | 1 +
> > drivers/clk/actions/owl-factor.c | 7 +-
> > drivers/mmc/host/Kconfig | 8 +
> > drivers/mmc/host/Makefile | 1 +
> > drivers/mmc/host/owl-mmc.c | 696 ++++++++++++++++++
> > 9 files changed, 877 insertions(+), 4 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> > create mode 100644 drivers/mmc/host/owl-mmc.c
> >
> > --
> > 2.17.1
> >
>
> I have picked up the mmc patches for next
Thanks :)
> and as Stephen picked the
> clock patch, the rest are now for arm-soc, I guess!?
>
Yes, I'll queue them through actions tree (unless Andreas wants to do the PR).
Regards,
Mani
> Kind regards
> Uffe
^ permalink raw reply [flat|nested] 21+ messages in thread