From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E76AC43331 for ; Thu, 7 Nov 2019 17:01:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E7632077C for ; Thu, 7 Nov 2019 17:01:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbfKGRBi (ORCPT ); Thu, 7 Nov 2019 12:01:38 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:33375 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726810AbfKGRBh (ORCPT ); Thu, 7 Nov 2019 12:01:37 -0500 Received: from litschi.hi.pengutronix.de ([2001:67c:670:100:feaa:14ff:fe6a:8db5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1iSlA4-0002mw-1W; Thu, 07 Nov 2019 18:01:32 +0100 Date: Thu, 7 Nov 2019 18:01:31 +0100 From: Michael Tretter To: Rajan Vaja Cc: mturquette@baylibre.com, sboyd@kernel.org, michal.simek@xilinx.com, jollys@xilinx.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jolly Shah , kernel@pengutronix.de Subject: Re: [PATCH] clk: zynqmp: Correct bit index for divider flag Message-ID: <20191107180131.63960cf1@litschi.hi.pengutronix.de> In-Reply-To: <1573117290-7990-1-git-send-email-rajan.vaja@xilinx.com> References: <1573117290-7990-1-git-send-email-rajan.vaja@xilinx.com> Organization: Pengutronix X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2001:67c:670:100:feaa:14ff:fe6a:8db5 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-clk@vger.kernel.org Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Thu, 07 Nov 2019 01:01:30 -0800, Rajan Vaja wrote: > Update divider flag bit index to match with firmware. > > Signed-off-by: Rajan Vaja > Signed-off-by: Jolly Shah > Signed-off-by: Michal Simek > --- > drivers/clk/zynqmp/divider.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c > index d8f5b70d..9e60834 100644 > --- a/drivers/clk/zynqmp/divider.c > +++ b/drivers/clk/zynqmp/divider.c > @@ -2,7 +2,7 @@ > /* > * Zynq UltraScale+ MPSoC Divider support > * > - * Copyright (C) 2016-2018 Xilinx > + * Copyright (C) 2016-2019 Xilinx > * > * Adjustable divider clock implementation > */ > @@ -25,7 +25,7 @@ > #define to_zynqmp_clk_divider(_hw) \ > container_of(_hw, struct zynqmp_clk_divider, hw) > > -#define CLK_FRAC BIT(13) /* has a fractional parent */ > +#define CLK_FRAC BIT(8) /* has a fractional parent */ NACK. This breaks the compatibility with the older/upstream versions of the TF-A. You have to at least make this dependent on the used version of the TF-A. > > /** > * struct zynqmp_clk_divider - adjustable divider clock