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* [PATCH] dt-bindings: clock: Add bindings for versal clock driver
@ 2019-11-07  7:16 Rajan Vaja
  2019-11-07 22:55 ` Stephen Boyd
  0 siblings, 1 reply; 2+ messages in thread
From: Rajan Vaja @ 2019-11-07  7:16 UTC (permalink / raw)
  To: mturquette, sboyd, robh+dt, mark.rutland
  Cc: linux-clk, devicetree, linux-kernel, Rajan Vaja, Jolly Shah,
	Michal Simek

Add documentation to describe Xilinx Versal clock driver
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 .../devicetree/bindings/clock/xlnx,versal-clk.txt  |  48 ++++++++
 include/dt-bindings/clock/xlnx-versal-clk.h        | 123 +++++++++++++++++++++
 2 files changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
 create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h

diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
new file mode 100644
index 0000000..398e751
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
@@ -0,0 +1,48 @@
+--------------------------------------------------------------------------
+Device Tree Clock bindings for the Xilinx Versal
+--------------------------------------------------------------------------
+The clock controller is a h/w block of Xilinx versal clock tree. It reads
+required input clock frequencies from the devicetree and acts as clock provider
+for all clock consumers of PS clocks.
+
+See clock_bindings.txt for more information on the generic clock bindings.
+
+Required properties:
+ - #clock-cells:	Must be 1
+ - compatible:		Must contain:	"xlnx,versal-clk"
+ - clocks:		List of clock specifiers which are external input
+			clocks to the given clock controller. Please refer
+			the next section to find the input clocks for a
+			given controller.
+ - clock-names:		List of clock names which are exteral input clocks
+			to the given clock controller. Please refer to the
+			clock bindings for more details.
+
+Input clocks for Xilinx Versal clock controller:
+
+The Xilinx Versal has one primary and two alternative reference clock inputs.
+These required clock inputs are:
+ - ref_clk
+ - alt_ref_clk
+ - pl_alt_ref_clk
+
+Output clocks are registered based on clock information received
+from firmware. Output clocks indexes are mentioned in
+include/dt-bindings/clock/xlnx-versal-clk.h.
+
+-------
+Example
+-------
+
+firmware {
+	versal_firmware: versal-firmware {
+		compatible = "xlnx,versal-firmware";
+		method = "smc";
+		versal_clk: clock-controller {
+			#clock-cells = <1>;
+			compatible = "xlnx,versal-clk";
+			clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
+			clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
new file mode 100644
index 0000000..264d634
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-versal-clk.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2019 Xilinx Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_VERSAL_H
+#define _DT_BINDINGS_CLK_VERSAL_H
+
+#define PMC_PLL					1
+#define APU_PLL					2
+#define RPU_PLL					3
+#define CPM_PLL					4
+#define NOC_PLL					5
+#define PLL_MAX					6
+#define PMC_PRESRC				7
+#define PMC_POSTCLK				8
+#define PMC_PLL_OUT				9
+#define PPLL					10
+#define NOC_PRESRC				11
+#define NOC_POSTCLK				12
+#define NOC_PLL_OUT				13
+#define NPLL					14
+#define APU_PRESRC				15
+#define APU_POSTCLK				16
+#define APU_PLL_OUT				17
+#define APLL					18
+#define RPU_PRESRC				19
+#define RPU_POSTCLK				20
+#define RPU_PLL_OUT				21
+#define RPLL					22
+#define CPM_PRESRC				23
+#define CPM_POSTCLK				24
+#define CPM_PLL_OUT				25
+#define CPLL					26
+#define PPLL_TO_XPD				27
+#define NPLL_TO_XPD				28
+#define APLL_TO_XPD				29
+#define RPLL_TO_XPD				30
+#define EFUSE_REF				31
+#define SYSMON_REF				32
+#define IRO_SUSPEND_REF				33
+#define USB_SUSPEND				34
+#define SWITCH_TIMEOUT				35
+#define RCLK_PMC				36
+#define RCLK_LPD				37
+#define WDT					38
+#define TTC0					39
+#define TTC1					40
+#define TTC2					41
+#define TTC3					42
+#define GEM_TSU					43
+#define GEM_TSU_LB				44
+#define MUXED_IRO_DIV2				45
+#define MUXED_IRO_DIV4				46
+#define PSM_REF					47
+#define GEM0_RX					48
+#define GEM0_TX					49
+#define GEM1_RX					50
+#define GEM1_TX					51
+#define CPM_CORE_REF				52
+#define CPM_LSBUS_REF				53
+#define CPM_DBG_REF				54
+#define CPM_AUX0_REF				55
+#define CPM_AUX1_REF				56
+#define QSPI_REF				57
+#define OSPI_REF				58
+#define SDIO0_REF				59
+#define SDIO1_REF				60
+#define PMC_LSBUS_REF				61
+#define I2C_REF					62
+#define TEST_PATTERN_REF			63
+#define DFT_OSC_REF				64
+#define PMC_PL0_REF				65
+#define PMC_PL1_REF				66
+#define PMC_PL2_REF				67
+#define PMC_PL3_REF				68
+#define CFU_REF					69
+#define SPARE_REF				70
+#define NPI_REF					71
+#define HSM0_REF				72
+#define HSM1_REF				73
+#define SD_DLL_REF				74
+#define FPD_TOP_SWITCH				75
+#define FPD_LSBUS				76
+#define ACPU					77
+#define DBG_TRACE				78
+#define DBG_FPD					79
+#define LPD_TOP_SWITCH				80
+#define ADMA					81
+#define LPD_LSBUS				82
+#define CPU_R5					83
+#define CPU_R5_CORE				84
+#define CPU_R5_OCM				85
+#define CPU_R5_OCM2				86
+#define IOU_SWITCH				87
+#define GEM0_REF				88
+#define GEM1_REF				89
+#define GEM_TSU_REF				90
+#define USB0_BUS_REF				91
+#define UART0_REF				92
+#define UART1_REF				93
+#define SPI0_REF				94
+#define SPI1_REF				95
+#define CAN0_REF				96
+#define CAN1_REF				97
+#define I2C0_REF				98
+#define I2C1_REF				99
+#define DBG_LPD					100
+#define TIMESTAMP_REF				101
+#define DBG_TSTMP				102
+#define CPM_TOPSW_REF				103
+#define USB3_DUAL_REF				104
+#define OUTCLK_MAX				105
+#define REF_CLK					106
+#define PL_ALT_REF_CLK				107
+#define MUXED_IRO				108
+#define PL_EXT					109
+#define PL_LB					110
+#define MIO_50_OR_51				111
+#define MIO_24_OR_25				112
+
+#endif
-- 
2.7.4


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] dt-bindings: clock: Add bindings for versal clock driver
  2019-11-07  7:16 [PATCH] dt-bindings: clock: Add bindings for versal clock driver Rajan Vaja
@ 2019-11-07 22:55 ` Stephen Boyd
  0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2019-11-07 22:55 UTC (permalink / raw)
  To: Rajan Vaja, mark.rutland, mturquette, robh+dt
  Cc: linux-clk, devicetree, linux-kernel, Rajan Vaja, Jolly Shah,
	Michal Simek

Quoting Rajan Vaja (2019-11-06 23:16:52)
> Add documentation to describe Xilinx Versal clock driver
> bindings.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Signoff chain is all wrong. The sender should come last. Please read up
on how to submit patches to the kernel with proper SoB chains in kernel
docs. I can dig it up if you can't find it.

> ---
>  .../devicetree/bindings/clock/xlnx,versal-clk.txt  |  48 ++++++++
>  include/dt-bindings/clock/xlnx-versal-clk.h        | 123 +++++++++++++++++++++
>  2 files changed, 171 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
>  create mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt
> new file mode 100644
> index 0000000..398e751
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt

Can you write this in YAML so we can validate it?

> @@ -0,0 +1,48 @@
> +--------------------------------------------------------------------------
> +Device Tree Clock bindings for the Xilinx Versal
> +--------------------------------------------------------------------------
> +The clock controller is a h/w block of Xilinx versal clock tree. It reads
> +required input clock frequencies from the devicetree and acts as clock provider
> +for all clock consumers of PS clocks.
> +
> +See clock_bindings.txt for more information on the generic clock bindings.
> +
> +Required properties:
> + - #clock-cells:       Must be 1
> + - compatible:         Must contain:   "xlnx,versal-clk"
> + - clocks:             List of clock specifiers which are external input
> +                       clocks to the given clock controller. Please refer
> +                       the next section to find the input clocks for a
> +                       given controller.
> + - clock-names:                List of clock names which are exteral input clocks
> +                       to the given clock controller. Please refer to the
> +                       clock bindings for more details.
> +
> +Input clocks for Xilinx Versal clock controller:
> +
> +The Xilinx Versal has one primary and two alternative reference clock inputs.
> +These required clock inputs are:
> + - ref_clk
> + - alt_ref_clk
> + - pl_alt_ref_clk
> +
> +Output clocks are registered based on clock information received
> +from firmware. Output clocks indexes are mentioned in
> +include/dt-bindings/clock/xlnx-versal-clk.h.
> +
> +-------
> +Example
> +-------
> +
> +firmware {
> +       versal_firmware: versal-firmware {
> +               compatible = "xlnx,versal-firmware";
> +               method = "smc";
> +               versal_clk: clock-controller {
> +                       #clock-cells = <1>;
> +                       compatible = "xlnx,versal-clk";
> +                       clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> +                       clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> +               };
> +       };
> +};
> diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
> new file mode 100644
> index 0000000..264d634
> --- /dev/null
> +++ b/include/dt-bindings/clock/xlnx-versal-clk.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + *  Copyright (C) 2019 Xilinx Inc.
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_VERSAL_H
> +#define _DT_BINDINGS_CLK_VERSAL_H
> +
> +#define PMC_PLL                                        1

Why not start with 0?


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2019-11-07  7:16 [PATCH] dt-bindings: clock: Add bindings for versal clock driver Rajan Vaja
2019-11-07 22:55 ` Stephen Boyd

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