From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Rongyi Chen <chenyi@tt-cool.com>, Icenowy Zheng <icenowy@aosc.io>,
Chen-Yu Tsai <wens@csie.org>, Sasha Levin <sashal@kernel.org>,
linux-clk@vger.kernel.org
Subject: [PATCH AUTOSEL 4.19 005/205] clk: sunxi-ng: h6: fix PWM gate/reset offset
Date: Fri, 8 Nov 2019 06:34:32 -0500 [thread overview]
Message-ID: <20191108113752.12502-5-sashal@kernel.org> (raw)
In-Reply-To: <20191108113752.12502-1-sashal@kernel.org>
From: Rongyi Chen <chenyi@tt-cool.com>
[ Upstream commit 58c0f79887d5e425fe6a9fd542778e50df69e9c6 ]
Currently the register offset of the PWM bus gate in Allwinner H6 clock
driver is wrong.
Fix this issue.
Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Rongyi Chen <chenyi@tt-cool.com>
[Icenowy: refactor commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 0f7a0ffd3f706..d425b47cef179 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -352,7 +352,7 @@ static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
0x79c, BIT(0), 0);
-static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x79c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
--
2.20.1
parent reply other threads:[~2019-11-08 12:15 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20191108113752.12502-1-sashal@kernel.org>]
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