* clk: X1000: Add support for the X1000.
@ 2019-10-18 17:50 Zhou Yanjie
2019-10-18 17:50 ` [PATCH 1/2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
` (3 more replies)
0 siblings, 4 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-18 17:50 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton, sboyd,
mark.rutland, syq, mturquette, paul
1.Add the clock bindings for X1000 from Ingenic.
2.Add support for the clocks provided by the CGU in the
Ingenic X1000 SoC.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/2] dt-bindings: clock: Add X1000 bindings.
2019-10-18 17:50 clk: X1000: Add support for the X1000 Zhou Yanjie
@ 2019-10-18 17:50 ` Zhou Yanjie
2019-10-18 17:50 ` [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
` (2 subsequent siblings)
3 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-18 17:50 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton, sboyd,
mark.rutland, syq, mturquette, paul
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1000-cgu.h | 41 ++++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 include/dt-bindings/clock/x1000-cgu.h
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
index ba5a442..75598e6 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -11,6 +11,7 @@ Required properties:
* ingenic,jz4725b-cgu
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
+ * ingenic,x1000-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 00000000..f0a1496
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1000 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_SCLKA 4
+#define X1000_CLK_CPUMUX 5
+#define X1000_CLK_CPU 6
+#define X1000_CLK_L2CACHE 7
+#define X1000_CLK_AHB0 8
+#define X1000_CLK_AHB2PMUX 9
+#define X1000_CLK_AHB2 10
+#define X1000_CLK_PCLK 11
+#define X1000_CLK_DDR 12
+#define X1000_CLK_MAC 13
+#define X1000_CLK_MSCMUX 14
+#define X1000_CLK_MSC0 15
+#define X1000_CLK_MSC1 16
+#define X1000_CLK_SSIPLL 17
+#define X1000_CLK_SSIMUX 18
+#define X1000_CLK_SFC 19
+#define X1000_CLK_UART0 20
+#define X1000_CLK_UART1 21
+#define X1000_CLK_UART2 22
+#define X1000_CLK_SSI 23
+#define X1000_CLK_PDMA 24
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000.
2019-10-18 17:50 clk: X1000: Add support for the X1000 Zhou Yanjie
2019-10-18 17:50 ` [PATCH 1/2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
@ 2019-10-18 17:50 ` Zhou Yanjie
2019-10-21 12:31 ` Paul Cercueil
2019-10-22 16:56 ` clk: X1000: Add support for the X1000 v2 Zhou Yanjie
2019-11-10 9:28 ` clk: X1000: Add support for the X1000 v3 Zhou Yanjie
3 siblings, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-18 17:50 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton, sboyd,
mark.rutland, syq, mturquette, paul
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/x1000-cgu.c | 253 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 264 insertions(+)
create mode 100644 drivers/clk/ingenic/x1000-cgu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index fe8db93..2aebf0d 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -45,4 +45,14 @@ config INGENIC_CGU_JZ4780
If building for a JZ4780 SoC, you want to say Y here.
+config INGENIC_CGU_X1000
+ bool "Ingenic X1000 CGU driver"
+ default MACH_X1000
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic X1000
+ and compatible SoCs.
+
+ If building for a X1000 SoC, you want to say Y here.
+
endmenu
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 250570a..0f0e784 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
+obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
new file mode 100644
index 00000000..c9d744c
--- /dev/null
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * X1000 SoC CGU driver
+ * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include "cgu.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_CLKGR 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_MACPHYCDR 0x54
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_I2SCDR1 0x70
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_CMP_INTR 0xb0
+#define CGU_REG_CMP_INTRE 0xb4
+#define CGU_REG_DRCG 0xd0
+#define CGU_REG_CLOCKSTATUS 0xd4
+#define CGU_REG_PCMCDR1 0xe0
+#define CGU_REG_MACPHYC 0xe8
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0 (1 << 7)
+#define OPCR_SPENDN1 (1 << 6)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[8] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+ [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [X1000_CLK_APLL] = {
+ "apll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_APLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ .stable_bit = 10,
+ },
+ },
+
+ [X1000_CLK_MPLL] = {
+ "mpll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_MPLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 6,
+ .enable_bit = 7,
+ .stable_bit = 0,
+ },
+ },
+
+ /* Muxes & dividers */
+
+ [X1000_CLK_SCLKA] = {
+ "sclk_a", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
+ .mux = { CGU_REG_CPCCR, 30, 2 },
+ },
+
+ [X1000_CLK_CPUMUX] = {
+ "cpu_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 28, 2 },
+ },
+
+ [X1000_CLK_CPU] = {
+ "cpu", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_L2CACHE] = {
+ "l2cache", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_AHB0] = {
+ "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 26, 2 },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
+ },
+
+ [X1000_CLK_AHB2PMUX] = {
+ "ahb2_apb_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 24, 2 },
+ },
+
+ [X1000_CLK_AHB2] = {
+ "ahb2", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_DDR] = {
+ "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_DDRCDR, 30, 2 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 31 },
+ },
+
+ [X1000_CLK_MAC] = {
+ "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MACPHYCDR, 31, 1 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 25 },
+ },
+
+ [X1000_CLK_MSCMUX] = {
+ "msc_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MSC0CDR, 31, 1 },
+ },
+
+ [X1000_CLK_MSC0] = {
+ "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 4 },
+ },
+
+ [X1000_CLK_MSC1] = {
+ "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 5 },
+ },
+
+ [X1000_CLK_SSIPLL] = {
+ "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 31, 1 },
+ .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
+ },
+
+ [X1000_CLK_SSIMUX] = {
+ "ssi_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 30, 1 },
+ },
+
+ /* Gate-only clocks */
+
+ [X1000_CLK_SFC] = {
+ "sfc", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 2 },
+ },
+
+ [X1000_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 14 },
+ },
+
+ [X1000_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 15 },
+ },
+
+ [X1000_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 16 },
+ },
+
+ [X1000_CLK_SSI] = {
+ "ssi", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 19 },
+ },
+
+ [X1000_CLK_PDMA] = {
+ "pdma", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 21 },
+ },
+};
+
+static void __init x1000_cgu_init(struct device_node *np)
+{
+ int retval;
+
+ cgu = ingenic_cgu_new(x1000_cgu_clocks,
+ ARRAY_SIZE(x1000_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval) {
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+ return;
+ }
+}
+CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000.
2019-10-18 17:50 ` [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
@ 2019-10-21 12:31 ` Paul Cercueil
2019-10-22 15:34 ` Zhou Yanjie
0 siblings, 1 reply; 22+ messages in thread
From: Paul Cercueil @ 2019-10-21 12:31 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, robh+dt,
paul.burton, sboyd, mark.rutland, syq, mturquette
Hi Zhou,
Le sam., oct. 19, 2019 at 01:50, Zhou Yanjie <zhouyanjie@zoho.com> a
écrit :
> Add support for the clocks provided by the CGU in the Ingenic X1000
> SoC, making use of the cgu code to do the heavy lifting.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
> drivers/clk/ingenic/Kconfig | 10 ++
> drivers/clk/ingenic/Makefile | 1 +
> drivers/clk/ingenic/x1000-cgu.c | 253
> ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 264 insertions(+)
> create mode 100644 drivers/clk/ingenic/x1000-cgu.c
>
> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
> index fe8db93..2aebf0d 100644
> --- a/drivers/clk/ingenic/Kconfig
> +++ b/drivers/clk/ingenic/Kconfig
> @@ -45,4 +45,14 @@ config INGENIC_CGU_JZ4780
>
> If building for a JZ4780 SoC, you want to say Y here.
>
> +config INGENIC_CGU_X1000
> + bool "Ingenic X1000 CGU driver"
> + default MACH_X1000
> + select INGENIC_CGU_COMMON
> + help
> + Support the clocks provided by the CGU hardware on Ingenic X1000
> + and compatible SoCs.
> +
> + If building for a X1000 SoC, you want to say Y here.
> +
> endmenu
> diff --git a/drivers/clk/ingenic/Makefile
> b/drivers/clk/ingenic/Makefile
> index 250570a..0f0e784 100644
> --- a/drivers/clk/ingenic/Makefile
> +++ b/drivers/clk/ingenic/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
> +obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
> diff --git a/drivers/clk/ingenic/x1000-cgu.c
> b/drivers/clk/ingenic/x1000-cgu.c
> new file mode 100644
> index 00000000..c9d744c
> --- /dev/null
> +++ b/drivers/clk/ingenic/x1000-cgu.c
> @@ -0,0 +1,253 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * X1000 SoC CGU driver
> + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <dt-bindings/clock/x1000-cgu.h>
> +#include "cgu.h"
> +
> +/* CGU register offsets */
> +#define CGU_REG_CPCCR 0x00
> +#define CGU_REG_APLL 0x10
> +#define CGU_REG_MPLL 0x14
> +#define CGU_REG_CLKGR 0x20
> +#define CGU_REG_OPCR 0x24
> +#define CGU_REG_DDRCDR 0x2c
> +#define CGU_REG_MACPHYCDR 0x54
> +#define CGU_REG_I2SCDR 0x60
> +#define CGU_REG_LPCDR 0x64
> +#define CGU_REG_MSC0CDR 0x68
> +#define CGU_REG_I2SCDR1 0x70
> +#define CGU_REG_SSICDR 0x74
> +#define CGU_REG_CIMCDR 0x7c
> +#define CGU_REG_PCMCDR 0x84
> +#define CGU_REG_MSC1CDR 0xa4
> +#define CGU_REG_CMP_INTR 0xb0
> +#define CGU_REG_CMP_INTRE 0xb4
> +#define CGU_REG_DRCG 0xd0
> +#define CGU_REG_CLOCKSTATUS 0xd4
> +#define CGU_REG_PCMCDR1 0xe0
> +#define CGU_REG_MACPHYC 0xe8
> +
> +/* bits within the OPCR register */
> +#define OPCR_SPENDN0 (1 << 7)
> +#define OPCR_SPENDN1 (1 << 6)
Please use the BIT() macro from <linux/bitops.h>
> +
> +static struct ingenic_cgu *cgu;
> +
> +static const s8 pll_od_encoding[8] = {
> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
> +};
> +
> +static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
> +
> + /* External clocks */
> +
> + [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
> + [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
> +
> + /* PLLs */
> +
> + [X1000_CLK_APLL] = {
> + "apll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_APLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 9,
> + .enable_bit = 8,
> + .stable_bit = 10,
> + },
> + },
> +
> + [X1000_CLK_MPLL] = {
> + "mpll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_MPLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 6,
> + .enable_bit = 7,
> + .stable_bit = 0,
> + },
> + },
> +
> + /* Muxes & dividers */
> +
> + [X1000_CLK_SCLKA] = {
> + "sclk_a", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
> + .mux = { CGU_REG_CPCCR, 30, 2 },
> + },
> +
> + [X1000_CLK_CPUMUX] = {
> + "cpu_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 28, 2 },
> + },
> +
> + [X1000_CLK_CPU] = {
> + "cpu", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_L2CACHE] = {
> + "l2cache", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB0] = {
> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 26, 2 },
> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB2PMUX] = {
> + "ahb2_apb_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 24, 2 },
> + },
> +
> + [X1000_CLK_AHB2] = {
> + "ahb2", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_PCLK] = {
> + "pclk", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_DDR] = {
> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_DDRCDR, 30, 2 },
> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 31 },
> + },
> +
> + [X1000_CLK_MAC] = {
> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MACPHYCDR, 31, 1 },
> + .div = { CGU_REG_DDRCDR, 0, 1, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 25 },
> + },
> +
> + [X1000_CLK_MSCMUX] = {
> + "msc_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MSC0CDR, 31, 1 },
> + },
> +
> + [X1000_CLK_MSC0] = {
> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 4 },
> + },
> +
> + [X1000_CLK_MSC1] = {
> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 5 },
> + },
> +
> + [X1000_CLK_SSIPLL] = {
> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 31, 1 },
> + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
> + },
> +
> + [X1000_CLK_SSIMUX] = {
> + "ssi_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 30, 1 },
> + },
> +
> + /* Gate-only clocks */
> +
> + [X1000_CLK_SFC] = {
> + "sfc", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 2 },
> + },
> +
> + [X1000_CLK_UART0] = {
> + "uart0", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 14 },
> + },
> +
> + [X1000_CLK_UART1] = {
> + "uart1", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 15 },
> + },
> +
> + [X1000_CLK_UART2] = {
> + "uart2", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 16 },
> + },
> +
> + [X1000_CLK_SSI] = {
> + "ssi", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 19 },
> + },
> +
> + [X1000_CLK_PDMA] = {
> + "pdma", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 21 },
> + },
> +};
> +
> +static void __init x1000_cgu_init(struct device_node *np)
> +{
> + int retval;
> +
> + cgu = ingenic_cgu_new(x1000_cgu_clocks,
> + ARRAY_SIZE(x1000_cgu_clocks), np);
> + if (!cgu) {
> + pr_err("%s: failed to initialise CGU\n", __func__);
> + return;
> + }
> +
> + retval = ingenic_cgu_register_clocks(cgu);
> + if (retval) {
> + pr_err("%s: failed to register CGU Clocks\n", __func__);
> + return;
Does this SoC has the LPM bit in the LCR register like on the other
SoCs?
If so, call ingenic_cgu_register_syscore_ops() here.
> + }
> +}
> +CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
Please use CLK_OF_DECLARE_DRIVER like the other CGU drivers.
Cheers,
-Paul
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000.
2019-10-21 12:31 ` Paul Cercueil
@ 2019-10-22 15:34 ` Zhou Yanjie
0 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-22 15:34 UTC (permalink / raw)
To: Paul Cercueil
Cc: linux-mips, linux-kernel, linux-clk, devicetree, robh+dt,
paul.burton, sboyd, mark.rutland, syq, mturquette
Hi Paul,
On 2019年10月21日 20:31, Paul Cercueil wrote:
> Hi Zhou,
>
>
> Le sam., oct. 19, 2019 at 01:50, Zhou Yanjie <zhouyanjie@zoho.com> a
> écrit :
>> Add support for the clocks provided by the CGU in the Ingenic X1000
>> SoC, making use of the cgu code to do the heavy lifting.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>> drivers/clk/ingenic/Kconfig | 10 ++
>> drivers/clk/ingenic/Makefile | 1 +
>> drivers/clk/ingenic/x1000-cgu.c | 253
>> ++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 264 insertions(+)
>> create mode 100644 drivers/clk/ingenic/x1000-cgu.c
>>
>> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
>> index fe8db93..2aebf0d 100644
>> --- a/drivers/clk/ingenic/Kconfig
>> +++ b/drivers/clk/ingenic/Kconfig
>> @@ -45,4 +45,14 @@ config INGENIC_CGU_JZ4780
>>
>> If building for a JZ4780 SoC, you want to say Y here.
>>
>> +config INGENIC_CGU_X1000
>> + bool "Ingenic X1000 CGU driver"
>> + default MACH_X1000
>> + select INGENIC_CGU_COMMON
>> + help
>> + Support the clocks provided by the CGU hardware on Ingenic X1000
>> + and compatible SoCs.
>> +
>> + If building for a X1000 SoC, you want to say Y here.
>> +
>> endmenu
>> diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
>> index 250570a..0f0e784 100644
>> --- a/drivers/clk/ingenic/Makefile
>> +++ b/drivers/clk/ingenic/Makefile
>> @@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
>> obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
>> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
>> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
>> +obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
>> diff --git a/drivers/clk/ingenic/x1000-cgu.c
>> b/drivers/clk/ingenic/x1000-cgu.c
>> new file mode 100644
>> index 00000000..c9d744c
>> --- /dev/null
>> +++ b/drivers/clk/ingenic/x1000-cgu.c
>> @@ -0,0 +1,253 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * X1000 SoC CGU driver
>> + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/delay.h>
>> +#include <linux/of.h>
>> +#include <dt-bindings/clock/x1000-cgu.h>
>> +#include "cgu.h"
>> +
>> +/* CGU register offsets */
>> +#define CGU_REG_CPCCR 0x00
>> +#define CGU_REG_APLL 0x10
>> +#define CGU_REG_MPLL 0x14
>> +#define CGU_REG_CLKGR 0x20
>> +#define CGU_REG_OPCR 0x24
>> +#define CGU_REG_DDRCDR 0x2c
>> +#define CGU_REG_MACPHYCDR 0x54
>> +#define CGU_REG_I2SCDR 0x60
>> +#define CGU_REG_LPCDR 0x64
>> +#define CGU_REG_MSC0CDR 0x68
>> +#define CGU_REG_I2SCDR1 0x70
>> +#define CGU_REG_SSICDR 0x74
>> +#define CGU_REG_CIMCDR 0x7c
>> +#define CGU_REG_PCMCDR 0x84
>> +#define CGU_REG_MSC1CDR 0xa4
>> +#define CGU_REG_CMP_INTR 0xb0
>> +#define CGU_REG_CMP_INTRE 0xb4
>> +#define CGU_REG_DRCG 0xd0
>> +#define CGU_REG_CLOCKSTATUS 0xd4
>> +#define CGU_REG_PCMCDR1 0xe0
>> +#define CGU_REG_MACPHYC 0xe8
>> +
>> +/* bits within the OPCR register */
>> +#define OPCR_SPENDN0 (1 << 7)
>> +#define OPCR_SPENDN1 (1 << 6)
>
> Please use the BIT() macro from <linux/bitops.h>
>
OK, I'll change it in v2.
>
>> +
>> +static struct ingenic_cgu *cgu;
>> +
>> +static const s8 pll_od_encoding[8] = {
>> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
>> +};
>> +
>> +static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
>> +
>> + /* External clocks */
>> +
>> + [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
>> + [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
>> +
>> + /* PLLs */
>> +
>> + [X1000_CLK_APLL] = {
>> + "apll", CGU_CLK_PLL,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .pll = {
>> + .reg = CGU_REG_APLL,
>> + .m_shift = 24,
>> + .m_bits = 7,
>> + .m_offset = 1,
>> + .n_shift = 18,
>> + .n_bits = 5,
>> + .n_offset = 1,
>> + .od_shift = 16,
>> + .od_bits = 2,
>> + .od_max = 8,
>> + .od_encoding = pll_od_encoding,
>> + .bypass_bit = 9,
>> + .enable_bit = 8,
>> + .stable_bit = 10,
>> + },
>> + },
>> +
>> + [X1000_CLK_MPLL] = {
>> + "mpll", CGU_CLK_PLL,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .pll = {
>> + .reg = CGU_REG_MPLL,
>> + .m_shift = 24,
>> + .m_bits = 7,
>> + .m_offset = 1,
>> + .n_shift = 18,
>> + .n_bits = 5,
>> + .n_offset = 1,
>> + .od_shift = 16,
>> + .od_bits = 2,
>> + .od_max = 8,
>> + .od_encoding = pll_od_encoding,
>> + .bypass_bit = 6,
>> + .enable_bit = 7,
>> + .stable_bit = 0,
>> + },
>> + },
>> +
>> + /* Muxes & dividers */
>> +
>> + [X1000_CLK_SCLKA] = {
>> + "sclk_a", CGU_CLK_MUX,
>> + .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
>> + .mux = { CGU_REG_CPCCR, 30, 2 },
>> + },
>> +
>> + [X1000_CLK_CPUMUX] = {
>> + "cpu_mux", CGU_CLK_MUX,
>> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
>> + .mux = { CGU_REG_CPCCR, 28, 2 },
>> + },
>> +
>> + [X1000_CLK_CPU] = {
>> + "cpu", CGU_CLK_DIV,
>> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
>> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
>> + },
>> +
>> + [X1000_CLK_L2CACHE] = {
>> + "l2cache", CGU_CLK_DIV,
>> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
>> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
>> + },
>> +
>> + [X1000_CLK_AHB0] = {
>> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
>> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
>> + .mux = { CGU_REG_CPCCR, 26, 2 },
>> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
>> + },
>> +
>> + [X1000_CLK_AHB2PMUX] = {
>> + "ahb2_apb_mux", CGU_CLK_MUX,
>> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
>> + .mux = { CGU_REG_CPCCR, 24, 2 },
>> + },
>> +
>> + [X1000_CLK_AHB2] = {
>> + "ahb2", CGU_CLK_DIV,
>> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
>> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
>> + },
>> +
>> + [X1000_CLK_PCLK] = {
>> + "pclk", CGU_CLK_DIV,
>> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
>> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
>> + },
>> +
>> + [X1000_CLK_DDR] = {
>> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
>> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
>> + .mux = { CGU_REG_DDRCDR, 30, 2 },
>> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
>> + .gate = { CGU_REG_CLKGR, 31 },
>> + },
>> +
>> + [X1000_CLK_MAC] = {
>> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
>> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
>> + .mux = { CGU_REG_MACPHYCDR, 31, 1 },
>> + .div = { CGU_REG_DDRCDR, 0, 1, 8, 29, 28, 27 },
>> + .gate = { CGU_REG_CLKGR, 25 },
>> + },
>> +
>> + [X1000_CLK_MSCMUX] = {
>> + "msc_mux", CGU_CLK_MUX,
>> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
>> + .mux = { CGU_REG_MSC0CDR, 31, 1 },
>> + },
>> +
>> + [X1000_CLK_MSC0] = {
>> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
>> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
>> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
>> + .gate = { CGU_REG_CLKGR, 4 },
>> + },
>> +
>> + [X1000_CLK_MSC1] = {
>> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
>> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
>> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
>> + .gate = { CGU_REG_CLKGR, 5 },
>> + },
>> +
>> + [X1000_CLK_SSIPLL] = {
>> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
>> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
>> + .mux = { CGU_REG_SSICDR, 31, 1 },
>> + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
>> + },
>> +
>> + [X1000_CLK_SSIMUX] = {
>> + "ssi_mux", CGU_CLK_MUX,
>> + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
>> + .mux = { CGU_REG_SSICDR, 30, 1 },
>> + },
>> +
>> + /* Gate-only clocks */
>> +
>> + [X1000_CLK_SFC] = {
>> + "sfc", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 2 },
>> + },
>> +
>> + [X1000_CLK_UART0] = {
>> + "uart0", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 14 },
>> + },
>> +
>> + [X1000_CLK_UART1] = {
>> + "uart1", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 15 },
>> + },
>> +
>> + [X1000_CLK_UART2] = {
>> + "uart2", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 16 },
>> + },
>> +
>> + [X1000_CLK_SSI] = {
>> + "ssi", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 19 },
>> + },
>> +
>> + [X1000_CLK_PDMA] = {
>> + "pdma", CGU_CLK_GATE,
>> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
>> + .gate = { CGU_REG_CLKGR, 21 },
>> + },
>> +};
>> +
>> +static void __init x1000_cgu_init(struct device_node *np)
>> +{
>> + int retval;
>> +
>> + cgu = ingenic_cgu_new(x1000_cgu_clocks,
>> + ARRAY_SIZE(x1000_cgu_clocks), np);
>> + if (!cgu) {
>> + pr_err("%s: failed to initialise CGU\n", __func__);
>> + return;
>> + }
>> +
>> + retval = ingenic_cgu_register_clocks(cgu);
>> + if (retval) {
>> + pr_err("%s: failed to register CGU Clocks\n", __func__);
>> + return;
>
> Does this SoC has the LPM bit in the LCR register like on the other SoCs?
> If so, call ingenic_cgu_register_syscore_ops() here.
>
Yes, it has, I'll change it in v2.
>
>> + }
>> +}
>> +CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
>
> Please use CLK_OF_DECLARE_DRIVER like the other CGU drivers.
>
sure, I'll change it in v2.
Best regards!
> Cheers,
> -Paul
>
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* clk: X1000: Add support for the X1000 v2.
2019-10-18 17:50 clk: X1000: Add support for the X1000 Zhou Yanjie
2019-10-18 17:50 ` [PATCH 1/2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-10-18 17:50 ` [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
@ 2019-10-22 16:56 ` Zhou Yanjie
2019-10-22 16:56 ` [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-10-22 16:56 ` [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
2019-11-10 9:28 ` clk: X1000: Add support for the X1000 v3 Zhou Yanjie
3 siblings, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-22 16:56 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton,
mturquette, sboyd, mark.rutland, paul
v1->v2:use BIT() macro instead left shift, add a call of
"ingenic_cgu_register_syscore_ops()", replace "CLK_OF_DECLARE"
with a "CLK_OF_DECLARE_DRIVER".
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings.
2019-10-22 16:56 ` clk: X1000: Add support for the X1000 v2 Zhou Yanjie
@ 2019-10-22 16:56 ` Zhou Yanjie
2019-10-25 21:49 ` Rob Herring
2019-10-22 16:56 ` [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
1 sibling, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-22 16:56 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton,
mturquette, sboyd, mark.rutland, paul
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1000-cgu.h | 41 ++++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 include/dt-bindings/clock/x1000-cgu.h
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
index ba5a442..75598e6 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -11,6 +11,7 @@ Required properties:
* ingenic,jz4725b-cgu
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
+ * ingenic,x1000-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 00000000..f0a1496
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1000 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_SCLKA 4
+#define X1000_CLK_CPUMUX 5
+#define X1000_CLK_CPU 6
+#define X1000_CLK_L2CACHE 7
+#define X1000_CLK_AHB0 8
+#define X1000_CLK_AHB2PMUX 9
+#define X1000_CLK_AHB2 10
+#define X1000_CLK_PCLK 11
+#define X1000_CLK_DDR 12
+#define X1000_CLK_MAC 13
+#define X1000_CLK_MSCMUX 14
+#define X1000_CLK_MSC0 15
+#define X1000_CLK_MSC1 16
+#define X1000_CLK_SSIPLL 17
+#define X1000_CLK_SSIMUX 18
+#define X1000_CLK_SFC 19
+#define X1000_CLK_UART0 20
+#define X1000_CLK_UART1 21
+#define X1000_CLK_UART2 22
+#define X1000_CLK_SSI 23
+#define X1000_CLK_PDMA 24
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000.
2019-10-22 16:56 ` clk: X1000: Add support for the X1000 v2 Zhou Yanjie
2019-10-22 16:56 ` [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
@ 2019-10-22 16:56 ` Zhou Yanjie
2019-11-02 21:27 ` Paul Cercueil
1 sibling, 1 reply; 22+ messages in thread
From: Zhou Yanjie @ 2019-10-22 16:56 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, robh+dt, paul.burton,
mturquette, sboyd, mark.rutland, paul
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/x1000-cgu.c | 256 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 267 insertions(+)
create mode 100644 drivers/clk/ingenic/x1000-cgu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index fe8db93..2aebf0d 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -45,4 +45,14 @@ config INGENIC_CGU_JZ4780
If building for a JZ4780 SoC, you want to say Y here.
+config INGENIC_CGU_X1000
+ bool "Ingenic X1000 CGU driver"
+ default MACH_X1000
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic X1000
+ and compatible SoCs.
+
+ If building for a X1000 SoC, you want to say Y here.
+
endmenu
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 250570a..0f0e784 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
+obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
new file mode 100644
index 00000000..a964911
--- /dev/null
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * X1000 SoC CGU driver
+ * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include "cgu.h"
+#include "pm.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_CLKGR 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_MACPHYCDR 0x54
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_I2SCDR1 0x70
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_CMP_INTR 0xb0
+#define CGU_REG_CMP_INTRE 0xb4
+#define CGU_REG_DRCG 0xd0
+#define CGU_REG_CLOCKSTATUS 0xd4
+#define CGU_REG_PCMCDR1 0xe0
+#define CGU_REG_MACPHYC 0xe8
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[8] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+ [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [X1000_CLK_APLL] = {
+ "apll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_APLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ .stable_bit = 10,
+ },
+ },
+
+ [X1000_CLK_MPLL] = {
+ "mpll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_MPLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 6,
+ .enable_bit = 7,
+ .stable_bit = 0,
+ },
+ },
+
+ /* Muxes & dividers */
+
+ [X1000_CLK_SCLKA] = {
+ "sclk_a", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
+ .mux = { CGU_REG_CPCCR, 30, 2 },
+ },
+
+ [X1000_CLK_CPUMUX] = {
+ "cpu_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 28, 2 },
+ },
+
+ [X1000_CLK_CPU] = {
+ "cpu", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_L2CACHE] = {
+ "l2cache", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_AHB0] = {
+ "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 26, 2 },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
+ },
+
+ [X1000_CLK_AHB2PMUX] = {
+ "ahb2_apb_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 24, 2 },
+ },
+
+ [X1000_CLK_AHB2] = {
+ "ahb2", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_DDR] = {
+ "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_DDRCDR, 30, 2 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 31 },
+ },
+
+ [X1000_CLK_MAC] = {
+ "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MACPHYCDR, 31, 1 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 25 },
+ },
+
+ [X1000_CLK_MSCMUX] = {
+ "msc_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MSC0CDR, 31, 1 },
+ },
+
+ [X1000_CLK_MSC0] = {
+ "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 4 },
+ },
+
+ [X1000_CLK_MSC1] = {
+ "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 5 },
+ },
+
+ [X1000_CLK_SSIPLL] = {
+ "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 31, 1 },
+ .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
+ },
+
+ [X1000_CLK_SSIMUX] = {
+ "ssi_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 30, 1 },
+ },
+
+ /* Gate-only clocks */
+
+ [X1000_CLK_SFC] = {
+ "sfc", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 2 },
+ },
+
+ [X1000_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 14 },
+ },
+
+ [X1000_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 15 },
+ },
+
+ [X1000_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 16 },
+ },
+
+ [X1000_CLK_SSI] = {
+ "ssi", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 19 },
+ },
+
+ [X1000_CLK_PDMA] = {
+ "pdma", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 21 },
+ },
+};
+
+static void __init x1000_cgu_init(struct device_node *np)
+{
+ int retval;
+
+ cgu = ingenic_cgu_new(x1000_cgu_clocks,
+ ARRAY_SIZE(x1000_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval) {
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+ return;
+ }
+
+ ingenic_cgu_register_syscore_ops(cgu);
+}
+CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings.
2019-10-22 16:56 ` [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
@ 2019-10-25 21:49 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2019-10-25 21:49 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, robh+dt,
paul.burton, mturquette, sboyd, mark.rutland, paul
On Wed, 23 Oct 2019 00:56:28 +0800, Zhou Yanjie wrote:
> Add the clock bindings for the X1000 Soc from Ingenic.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
> include/dt-bindings/clock/x1000-cgu.h | 41 ++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000.
2019-10-22 16:56 ` [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
@ 2019-11-02 21:27 ` Paul Cercueil
0 siblings, 0 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-11-02 21:27 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, robh+dt,
paul.burton, mturquette, sboyd, mark.rutland
Hi,
Le mer., oct. 23, 2019 at 00:56, Zhou Yanjie <zhouyanjie@zoho.com> a
écrit :
> Add support for the clocks provided by the CGU in the Ingenic X1000
> SoC, making use of the cgu code to do the heavy lifting.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
> drivers/clk/ingenic/Kconfig | 10 ++
> drivers/clk/ingenic/Makefile | 1 +
> drivers/clk/ingenic/x1000-cgu.c | 256
> ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 267 insertions(+)
> create mode 100644 drivers/clk/ingenic/x1000-cgu.c
>
> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
> index fe8db93..2aebf0d 100644
> --- a/drivers/clk/ingenic/Kconfig
> +++ b/drivers/clk/ingenic/Kconfig
> @@ -45,4 +45,14 @@ config INGENIC_CGU_JZ4780
>
> If building for a JZ4780 SoC, you want to say Y here.
>
> +config INGENIC_CGU_X1000
> + bool "Ingenic X1000 CGU driver"
> + default MACH_X1000
> + select INGENIC_CGU_COMMON
> + help
> + Support the clocks provided by the CGU hardware on Ingenic X1000
> + and compatible SoCs.
> +
> + If building for a X1000 SoC, you want to say Y here.
> +
> endmenu
> diff --git a/drivers/clk/ingenic/Makefile
> b/drivers/clk/ingenic/Makefile
> index 250570a..0f0e784 100644
> --- a/drivers/clk/ingenic/Makefile
> +++ b/drivers/clk/ingenic/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
> +obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
> diff --git a/drivers/clk/ingenic/x1000-cgu.c
> b/drivers/clk/ingenic/x1000-cgu.c
> new file mode 100644
> index 00000000..a964911
> --- /dev/null
> +++ b/drivers/clk/ingenic/x1000-cgu.c
> @@ -0,0 +1,256 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * X1000 SoC CGU driver
> + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <dt-bindings/clock/x1000-cgu.h>
> +#include "cgu.h"
> +#include "pm.h"
> +
> +/* CGU register offsets */
> +#define CGU_REG_CPCCR 0x00
> +#define CGU_REG_APLL 0x10
> +#define CGU_REG_MPLL 0x14
> +#define CGU_REG_CLKGR 0x20
> +#define CGU_REG_OPCR 0x24
> +#define CGU_REG_DDRCDR 0x2c
> +#define CGU_REG_MACPHYCDR 0x54
> +#define CGU_REG_I2SCDR 0x60
> +#define CGU_REG_LPCDR 0x64
> +#define CGU_REG_MSC0CDR 0x68
> +#define CGU_REG_I2SCDR1 0x70
> +#define CGU_REG_SSICDR 0x74
> +#define CGU_REG_CIMCDR 0x7c
> +#define CGU_REG_PCMCDR 0x84
> +#define CGU_REG_MSC1CDR 0xa4
> +#define CGU_REG_CMP_INTR 0xb0
> +#define CGU_REG_CMP_INTRE 0xb4
> +#define CGU_REG_DRCG 0xd0
> +#define CGU_REG_CLOCKSTATUS 0xd4
> +#define CGU_REG_PCMCDR1 0xe0
> +#define CGU_REG_MACPHYC 0xe8
> +
> +/* bits within the OPCR register */
> +#define OPCR_SPENDN0 BIT(7)
> +#define OPCR_SPENDN1 BIT(6)
> +
> +static struct ingenic_cgu *cgu;
> +
> +static const s8 pll_od_encoding[8] = {
> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
> +};
> +
> +static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
> +
> + /* External clocks */
> +
> + [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
> + [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
> +
> + /* PLLs */
> +
> + [X1000_CLK_APLL] = {
> + "apll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_APLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 9,
> + .enable_bit = 8,
> + .stable_bit = 10,
> + },
> + },
> +
> + [X1000_CLK_MPLL] = {
> + "mpll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_MPLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 6,
> + .enable_bit = 7,
> + .stable_bit = 0,
> + },
> + },
> +
> + /* Muxes & dividers */
> +
> + [X1000_CLK_SCLKA] = {
> + "sclk_a", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
> + .mux = { CGU_REG_CPCCR, 30, 2 },
> + },
> +
> + [X1000_CLK_CPUMUX] = {
> + "cpu_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 28, 2 },
> + },
> +
> + [X1000_CLK_CPU] = {
> + "cpu", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_L2CACHE] = {
> + "l2cache", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB0] = {
> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 26, 2 },
> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB2PMUX] = {
> + "ahb2_apb_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 24, 2 },
> + },
> +
> + [X1000_CLK_AHB2] = {
> + "ahb2", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_PCLK] = {
> + "pclk", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_DDR] = {
> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_DDRCDR, 30, 2 },
> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 31 },
> + },
> +
> + [X1000_CLK_MAC] = {
> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MACPHYCDR, 31, 1 },
> + .div = { CGU_REG_DDRCDR, 0, 1, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 25 },
> + },
> +
> + [X1000_CLK_MSCMUX] = {
> + "msc_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MSC0CDR, 31, 1 },
> + },
> +
> + [X1000_CLK_MSC0] = {
> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 4 },
> + },
> +
> + [X1000_CLK_MSC1] = {
> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 5 },
> + },
> +
> + [X1000_CLK_SSIPLL] = {
> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 31, 1 },
> + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
> + },
> +
> + [X1000_CLK_SSIMUX] = {
> + "ssi_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 30, 1 },
> + },
> +
> + /* Gate-only clocks */
> +
> + [X1000_CLK_SFC] = {
> + "sfc", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 2 },
> + },
> +
> + [X1000_CLK_UART0] = {
> + "uart0", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 14 },
> + },
> +
> + [X1000_CLK_UART1] = {
> + "uart1", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 15 },
> + },
> +
> + [X1000_CLK_UART2] = {
> + "uart2", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 16 },
> + },
> +
> + [X1000_CLK_SSI] = {
> + "ssi", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 19 },
> + },
> +
> + [X1000_CLK_PDMA] = {
> + "pdma", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 21 },
> + },
> +};
> +
> +static void __init x1000_cgu_init(struct device_node *np)
> +{
> + int retval;
> +
> + cgu = ingenic_cgu_new(x1000_cgu_clocks,
> + ARRAY_SIZE(x1000_cgu_clocks), np);
> + if (!cgu) {
> + pr_err("%s: failed to initialise CGU\n", __func__);
> + return;
> + }
> +
> + retval = ingenic_cgu_register_clocks(cgu);
> + if (retval) {
> + pr_err("%s: failed to register CGU Clocks\n", __func__);
> + return;
> + }
> +
> + ingenic_cgu_register_syscore_ops(cgu);
> +}
> +CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu",
> x1000_cgu_init);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* clk: X1000: Add support for the X1000 v3
2019-10-18 17:50 clk: X1000: Add support for the X1000 Zhou Yanjie
` (2 preceding siblings ...)
2019-10-22 16:56 ` clk: X1000: Add support for the X1000 v2 Zhou Yanjie
@ 2019-11-10 9:28 ` Zhou Yanjie
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-11-10 9:28 ` [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
3 siblings, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-10 9:28 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, mturquette, paul.burton,
sboyd, robh+dt, syq, mark.rutland, paul
v1:
1.Add the clock bindings for X1000 from Ingenic.
2.Add support for the clocks provided by the CGU in the
Ingenic X1000 SoC.
v1->v2:
use BIT() macro instead left shift, add a call of
"ingenic_cgu_register_syscore_ops()", replace "CLK_OF_DECLARE"
with a "CLK_OF_DECLARE_DRIVER".
v2->v3:
1.Modify the wrong register in "X1000_CLK_MAC".
2.Add the clock of I2C0~I2C2.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-10 9:28 ` clk: X1000: Add support for the X1000 v3 Zhou Yanjie
@ 2019-11-10 9:28 ` Zhou Yanjie
2019-11-11 1:13 ` Paul Cercueil
` (2 more replies)
2019-11-10 9:28 ` [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
1 sibling, 3 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-10 9:28 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, mturquette, paul.burton,
sboyd, robh+dt, syq, mark.rutland, paul
Add the clock bindings for the X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 include/dt-bindings/clock/x1000-cgu.h
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
index ba5a442..75598e6 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
@@ -11,6 +11,7 @@ Required properties:
* ingenic,jz4725b-cgu
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
+ * ingenic,x1000-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 00000000..bbaebaf
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1000 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_SCLKA 4
+#define X1000_CLK_CPUMUX 5
+#define X1000_CLK_CPU 6
+#define X1000_CLK_L2CACHE 7
+#define X1000_CLK_AHB0 8
+#define X1000_CLK_AHB2PMUX 9
+#define X1000_CLK_AHB2 10
+#define X1000_CLK_PCLK 11
+#define X1000_CLK_DDR 12
+#define X1000_CLK_MAC 13
+#define X1000_CLK_MSCMUX 14
+#define X1000_CLK_MSC0 15
+#define X1000_CLK_MSC1 16
+#define X1000_CLK_SSIPLL 17
+#define X1000_CLK_SSIMUX 18
+#define X1000_CLK_SFC 19
+#define X1000_CLK_I2C0 20
+#define X1000_CLK_I2C1 21
+#define X1000_CLK_I2C2 22
+#define X1000_CLK_UART0 23
+#define X1000_CLK_UART1 24
+#define X1000_CLK_UART2 25
+#define X1000_CLK_SSI 26
+#define X1000_CLK_PDMA 27
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000.
2019-11-10 9:28 ` clk: X1000: Add support for the X1000 v3 Zhou Yanjie
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
@ 2019-11-10 9:28 ` Zhou Yanjie
2019-11-11 1:16 ` Paul Cercueil
2019-11-14 0:00 ` Stephen Boyd
1 sibling, 2 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-10 9:28 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, linux-clk, devicetree, mturquette, paul.burton,
sboyd, robh+dt, syq, mark.rutland, paul
Add support for the clocks provided by the CGU in the Ingenic X1000
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/x1000-cgu.c | 274 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 285 insertions(+)
create mode 100644 drivers/clk/ingenic/x1000-cgu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 1cb4899..fb7b399 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -45,6 +45,16 @@ config INGENIC_CGU_JZ4780
If building for a JZ4780 SoC, you want to say Y here.
+config INGENIC_CGU_X1000
+ bool "Ingenic X1000 CGU driver"
+ default MACH_X1000
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic X1000
+ and compatible SoCs.
+
+ If building for a X1000 SoC, you want to say Y here.
+
config INGENIC_TCU_CLK
bool "Ingenic JZ47xx TCU clocks driver"
default MACH_INGENIC
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 097220b..8b1dad9 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
+obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
new file mode 100644
index 00000000..b22d87b
--- /dev/null
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * X1000 SoC CGU driver
+ * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include "cgu.h"
+#include "pm.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_CLKGR 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_MACCDR 0x54
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_I2SCDR1 0x70
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_CMP_INTR 0xb0
+#define CGU_REG_CMP_INTRE 0xb4
+#define CGU_REG_DRCG 0xd0
+#define CGU_REG_CPCSR 0xd4
+#define CGU_REG_PCMCDR1 0xe0
+#define CGU_REG_MACPHYC 0xe8
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[8] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+ [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [X1000_CLK_APLL] = {
+ "apll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_APLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ .stable_bit = 10,
+ },
+ },
+
+ [X1000_CLK_MPLL] = {
+ "mpll", CGU_CLK_PLL,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_MPLL,
+ .m_shift = 24,
+ .m_bits = 7,
+ .m_offset = 1,
+ .n_shift = 18,
+ .n_bits = 5,
+ .n_offset = 1,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = 6,
+ .enable_bit = 7,
+ .stable_bit = 0,
+ },
+ },
+
+ /* Muxes & dividers */
+
+ [X1000_CLK_SCLKA] = {
+ "sclk_a", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
+ .mux = { CGU_REG_CPCCR, 30, 2 },
+ },
+
+ [X1000_CLK_CPUMUX] = {
+ "cpu_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 28, 2 },
+ },
+
+ [X1000_CLK_CPU] = {
+ "cpu", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_L2CACHE] = {
+ "l2cache", CGU_CLK_DIV,
+ .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+ },
+
+ [X1000_CLK_AHB0] = {
+ "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 26, 2 },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
+ },
+
+ [X1000_CLK_AHB2PMUX] = {
+ "ahb2_apb_mux", CGU_CLK_MUX,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 24, 2 },
+ },
+
+ [X1000_CLK_AHB2] = {
+ "ahb2", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
+ },
+
+ [X1000_CLK_DDR] = {
+ "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+ .mux = { CGU_REG_DDRCDR, 30, 2 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 31 },
+ },
+
+ [X1000_CLK_MAC] = {
+ "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MACCDR, 31, 1 },
+ .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 25 },
+ },
+
+ [X1000_CLK_MSCMUX] = {
+ "msc_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .mux = { CGU_REG_MSC0CDR, 31, 1 },
+ },
+
+ [X1000_CLK_MSC0] = {
+ "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 4 },
+ },
+
+ [X1000_CLK_MSC1] = {
+ "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 5 },
+ },
+
+ [X1000_CLK_SSIPLL] = {
+ "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 31, 1 },
+ .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
+ },
+
+ [X1000_CLK_SSIMUX] = {
+ "ssi_mux", CGU_CLK_MUX,
+ .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 30, 1 },
+ },
+
+ /* Gate-only clocks */
+
+ [X1000_CLK_SFC] = {
+ "sfc", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 2 },
+ },
+
+ [X1000_CLK_I2C0] = {
+ "i2c0", CGU_CLK_GATE,
+ .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 7 },
+ },
+
+ [X1000_CLK_I2C1] = {
+ "i2c1", CGU_CLK_GATE,
+ .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 8 },
+ },
+
+ [X1000_CLK_I2C2] = {
+ "i2c2", CGU_CLK_GATE,
+ .parents = { X1000_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 9 },
+ },
+
+ [X1000_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 14 },
+ },
+
+ [X1000_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 15 },
+ },
+
+ [X1000_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 16 },
+ },
+
+ [X1000_CLK_SSI] = {
+ "ssi", CGU_CLK_GATE,
+ .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 19 },
+ },
+
+ [X1000_CLK_PDMA] = {
+ "pdma", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 21 },
+ },
+};
+
+static void __init x1000_cgu_init(struct device_node *np)
+{
+ int retval;
+
+ cgu = ingenic_cgu_new(x1000_cgu_clocks,
+ ARRAY_SIZE(x1000_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval) {
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+ return;
+ }
+
+ ingenic_cgu_register_syscore_ops(cgu);
+}
+CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
@ 2019-11-11 1:13 ` Paul Cercueil
2019-11-14 13:25 ` Zhou Yanjie
2019-11-12 0:55 ` Rob Herring
2019-11-14 0:00 ` Stephen Boyd
2 siblings, 1 reply; 22+ messages in thread
From: Paul Cercueil @ 2019-11-11 1:13 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, sboyd, robh+dt, syq, mark.rutland
Hi Zhou,
Le dim., nov. 10, 2019 at 17:28, Zhou Yanjie <zhouyanjie@zoho.com> a
écrit :
> Add the clock bindings for the X1000 Soc from Ingenic.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
> ---
> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
> include/dt-bindings/clock/x1000-cgu.h | 44
> ++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
When you send a revised version of a patchset, it's common practice to
have a per-patch changelog right here. Then a cover letter is only
really needed for big patchsets that need extra information.
>
> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> index ba5a442..75598e6 100644
> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
> @@ -11,6 +11,7 @@ Required properties:
> * ingenic,jz4725b-cgu
> * ingenic,jz4770-cgu
> * ingenic,jz4780-cgu
> + * ingenic,x1000-cgu
> - reg : The address & length of the CGU registers.
> - clocks : List of phandle & clock specifiers for clocks external to
> the CGU.
> Two such external clocks should be specified - first the external
> crystal
> diff --git a/include/dt-bindings/clock/x1000-cgu.h
> b/include/dt-bindings/clock/x1000-cgu.h
> new file mode 100644
> index 00000000..bbaebaf
> --- /dev/null
> +++ b/include/dt-bindings/clock/x1000-cgu.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides clock numbers for the ingenic,x1000-cgu DT
> binding.
> + *
> + * They are roughly ordered as:
> + * - external clocks
> + * - PLLs
> + * - muxes/dividers in the order they appear in the x1000
> programmers manual
> + * - gates in order of their bit in the CLKGR* registers
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
> +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
> +
> +#define X1000_CLK_EXCLK 0
> +#define X1000_CLK_RTCLK 1
> +#define X1000_CLK_APLL 2
> +#define X1000_CLK_MPLL 3
> +#define X1000_CLK_SCLKA 4
> +#define X1000_CLK_CPUMUX 5
> +#define X1000_CLK_CPU 6
> +#define X1000_CLK_L2CACHE 7
> +#define X1000_CLK_AHB0 8
> +#define X1000_CLK_AHB2PMUX 9
> +#define X1000_CLK_AHB2 10
> +#define X1000_CLK_PCLK 11
> +#define X1000_CLK_DDR 12
> +#define X1000_CLK_MAC 13
> +#define X1000_CLK_MSCMUX 14
> +#define X1000_CLK_MSC0 15
> +#define X1000_CLK_MSC1 16
> +#define X1000_CLK_SSIPLL 17
> +#define X1000_CLK_SSIMUX 18
> +#define X1000_CLK_SFC 19
> +#define X1000_CLK_I2C0 20
> +#define X1000_CLK_I2C1 21
> +#define X1000_CLK_I2C2 22
> +#define X1000_CLK_UART0 23
> +#define X1000_CLK_UART1 24
> +#define X1000_CLK_UART2 25
> +#define X1000_CLK_SSI 26
> +#define X1000_CLK_PDMA 27
> +
> +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000.
2019-11-10 9:28 ` [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
@ 2019-11-11 1:16 ` Paul Cercueil
2019-11-14 0:00 ` Stephen Boyd
1 sibling, 0 replies; 22+ messages in thread
From: Paul Cercueil @ 2019-11-11 1:16 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, sboyd, robh+dt, syq, mark.rutland
Hi,
Le dim., nov. 10, 2019 at 17:28, Zhou Yanjie <zhouyanjie@zoho.com> a
écrit :
> Add support for the clocks provided by the CGU in the Ingenic X1000
> SoC, making use of the cgu code to do the heavy lifting.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/clk/ingenic/Kconfig | 10 ++
> drivers/clk/ingenic/Makefile | 1 +
> drivers/clk/ingenic/x1000-cgu.c | 274
> ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 285 insertions(+)
> create mode 100644 drivers/clk/ingenic/x1000-cgu.c
>
> diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
> index 1cb4899..fb7b399 100644
> --- a/drivers/clk/ingenic/Kconfig
> +++ b/drivers/clk/ingenic/Kconfig
> @@ -45,6 +45,16 @@ config INGENIC_CGU_JZ4780
>
> If building for a JZ4780 SoC, you want to say Y here.
>
> +config INGENIC_CGU_X1000
> + bool "Ingenic X1000 CGU driver"
> + default MACH_X1000
> + select INGENIC_CGU_COMMON
> + help
> + Support the clocks provided by the CGU hardware on Ingenic X1000
> + and compatible SoCs.
> +
> + If building for a X1000 SoC, you want to say Y here.
> +
> config INGENIC_TCU_CLK
> bool "Ingenic JZ47xx TCU clocks driver"
> default MACH_INGENIC
> diff --git a/drivers/clk/ingenic/Makefile
> b/drivers/clk/ingenic/Makefile
> index 097220b..8b1dad9 100644
> --- a/drivers/clk/ingenic/Makefile
> +++ b/drivers/clk/ingenic/Makefile
> @@ -4,4 +4,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
> obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
> +obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
> obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
> diff --git a/drivers/clk/ingenic/x1000-cgu.c
> b/drivers/clk/ingenic/x1000-cgu.c
> new file mode 100644
> index 00000000..b22d87b
> --- /dev/null
> +++ b/drivers/clk/ingenic/x1000-cgu.c
> @@ -0,0 +1,274 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * X1000 SoC CGU driver
> + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <linux/of.h>
> +#include <dt-bindings/clock/x1000-cgu.h>
> +#include "cgu.h"
> +#include "pm.h"
> +
> +/* CGU register offsets */
> +#define CGU_REG_CPCCR 0x00
> +#define CGU_REG_APLL 0x10
> +#define CGU_REG_MPLL 0x14
> +#define CGU_REG_CLKGR 0x20
> +#define CGU_REG_OPCR 0x24
> +#define CGU_REG_DDRCDR 0x2c
> +#define CGU_REG_MACCDR 0x54
> +#define CGU_REG_I2SCDR 0x60
> +#define CGU_REG_LPCDR 0x64
> +#define CGU_REG_MSC0CDR 0x68
> +#define CGU_REG_I2SCDR1 0x70
> +#define CGU_REG_SSICDR 0x74
> +#define CGU_REG_CIMCDR 0x7c
> +#define CGU_REG_PCMCDR 0x84
> +#define CGU_REG_MSC1CDR 0xa4
> +#define CGU_REG_CMP_INTR 0xb0
> +#define CGU_REG_CMP_INTRE 0xb4
> +#define CGU_REG_DRCG 0xd0
> +#define CGU_REG_CPCSR 0xd4
> +#define CGU_REG_PCMCDR1 0xe0
> +#define CGU_REG_MACPHYC 0xe8
> +
> +/* bits within the OPCR register */
> +#define OPCR_SPENDN0 BIT(7)
> +#define OPCR_SPENDN1 BIT(6)
> +
> +static struct ingenic_cgu *cgu;
> +
> +static const s8 pll_od_encoding[8] = {
> + 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
> +};
> +
> +static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
> +
> + /* External clocks */
> +
> + [X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
> + [X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
> +
> + /* PLLs */
> +
> + [X1000_CLK_APLL] = {
> + "apll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_APLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 9,
> + .enable_bit = 8,
> + .stable_bit = 10,
> + },
> + },
> +
> + [X1000_CLK_MPLL] = {
> + "mpll", CGU_CLK_PLL,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .pll = {
> + .reg = CGU_REG_MPLL,
> + .m_shift = 24,
> + .m_bits = 7,
> + .m_offset = 1,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 1,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 8,
> + .od_encoding = pll_od_encoding,
> + .bypass_bit = 6,
> + .enable_bit = 7,
> + .stable_bit = 0,
> + },
> + },
> +
> + /* Muxes & dividers */
> +
> + [X1000_CLK_SCLKA] = {
> + "sclk_a", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
> + .mux = { CGU_REG_CPCCR, 30, 2 },
> + },
> +
> + [X1000_CLK_CPUMUX] = {
> + "cpu_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 28, 2 },
> + },
> +
> + [X1000_CLK_CPU] = {
> + "cpu", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_L2CACHE] = {
> + "l2cache", CGU_CLK_DIV,
> + .parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB0] = {
> + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 26, 2 },
> + .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
> + },
> +
> + [X1000_CLK_AHB2PMUX] = {
> + "ahb2_apb_mux", CGU_CLK_MUX,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_CPCCR, 24, 2 },
> + },
> +
> + [X1000_CLK_AHB2] = {
> + "ahb2", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_PCLK] = {
> + "pclk", CGU_CLK_DIV,
> + .parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
> + .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
> + },
> +
> + [X1000_CLK_DDR] = {
> + "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
> + .mux = { CGU_REG_DDRCDR, 30, 2 },
> + .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 31 },
> + },
> +
> + [X1000_CLK_MAC] = {
> + "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MACCDR, 31, 1 },
> + .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 25 },
> + },
> +
> + [X1000_CLK_MSCMUX] = {
> + "msc_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
> + .mux = { CGU_REG_MSC0CDR, 31, 1 },
> + },
> +
> + [X1000_CLK_MSC0] = {
> + "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 4 },
> + },
> +
> + [X1000_CLK_MSC1] = {
> + "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
> + .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
> + .gate = { CGU_REG_CLKGR, 5 },
> + },
> +
> + [X1000_CLK_SSIPLL] = {
> + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 31, 1 },
> + .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
> + },
> +
> + [X1000_CLK_SSIMUX] = {
> + "ssi_mux", CGU_CLK_MUX,
> + .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
> + .mux = { CGU_REG_SSICDR, 30, 1 },
> + },
> +
> + /* Gate-only clocks */
> +
> + [X1000_CLK_SFC] = {
> + "sfc", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 2 },
> + },
> +
> + [X1000_CLK_I2C0] = {
> + "i2c0", CGU_CLK_GATE,
> + .parents = { X1000_CLK_PCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 7 },
> + },
> +
> + [X1000_CLK_I2C1] = {
> + "i2c1", CGU_CLK_GATE,
> + .parents = { X1000_CLK_PCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 8 },
> + },
> +
> + [X1000_CLK_I2C2] = {
> + "i2c2", CGU_CLK_GATE,
> + .parents = { X1000_CLK_PCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 9 },
> + },
> +
> + [X1000_CLK_UART0] = {
> + "uart0", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 14 },
> + },
> +
> + [X1000_CLK_UART1] = {
> + "uart1", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 15 },
> + },
> +
> + [X1000_CLK_UART2] = {
> + "uart2", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 16 },
> + },
> +
> + [X1000_CLK_SSI] = {
> + "ssi", CGU_CLK_GATE,
> + .parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 19 },
> + },
> +
> + [X1000_CLK_PDMA] = {
> + "pdma", CGU_CLK_GATE,
> + .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 21 },
> + },
> +};
> +
> +static void __init x1000_cgu_init(struct device_node *np)
> +{
> + int retval;
> +
> + cgu = ingenic_cgu_new(x1000_cgu_clocks,
> + ARRAY_SIZE(x1000_cgu_clocks), np);
> + if (!cgu) {
> + pr_err("%s: failed to initialise CGU\n", __func__);
> + return;
> + }
> +
> + retval = ingenic_cgu_register_clocks(cgu);
> + if (retval) {
> + pr_err("%s: failed to register CGU Clocks\n", __func__);
> + return;
> + }
> +
> + ingenic_cgu_register_syscore_ops(cgu);
> +}
> +CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-11-11 1:13 ` Paul Cercueil
@ 2019-11-12 0:55 ` Rob Herring
2019-11-13 23:59 ` Stephen Boyd
2019-11-14 13:29 ` Zhou Yanjie
2019-11-14 0:00 ` Stephen Boyd
2 siblings, 2 replies; 22+ messages in thread
From: Rob Herring @ 2019-11-12 0:55 UTC (permalink / raw)
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, sboyd, robh+dt, syq, mark.rutland, paul
On Sun, 10 Nov 2019 17:28:21 +0800, Zhou Yanjie wrote:
> Add the clock bindings for the X1000 Soc from Ingenic.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
> include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-12 0:55 ` Rob Herring
@ 2019-11-13 23:59 ` Stephen Boyd
2019-11-14 13:37 ` Zhou Yanjie
2019-11-14 13:29 ` Zhou Yanjie
1 sibling, 1 reply; 22+ messages in thread
From: Stephen Boyd @ 2019-11-13 23:59 UTC (permalink / raw)
To: Rob Herring, Zhou Yanjie
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, robh+dt, syq, mark.rutland, paul
Quoting Rob Herring (2019-11-11 16:55:44)
> On Sun, 10 Nov 2019 17:28:21 +0800, Zhou Yanjie wrote:
> > Add the clock bindings for the X1000 Soc from Ingenic.
> >
> > Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> > ---
> > .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
> > include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++
> > 2 files changed, 45 insertions(+)
> > create mode 100644 include/dt-bindings/clock/x1000-cgu.h
> >
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
It looks like some extra defines were added. I carried forward your
review tag.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-11-11 1:13 ` Paul Cercueil
2019-11-12 0:55 ` Rob Herring
@ 2019-11-14 0:00 ` Stephen Boyd
2 siblings, 0 replies; 22+ messages in thread
From: Stephen Boyd @ 2019-11-14 0:00 UTC (permalink / raw)
To: Zhou Yanjie, linux-mips
Cc: linux-kernel, linux-clk, devicetree, mturquette, paul.burton,
robh+dt, syq, mark.rutland, paul
Quoting Zhou Yanjie (2019-11-10 01:28:21)
> Add the clock bindings for the X1000 Soc from Ingenic.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000.
2019-11-10 9:28 ` [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
2019-11-11 1:16 ` Paul Cercueil
@ 2019-11-14 0:00 ` Stephen Boyd
1 sibling, 0 replies; 22+ messages in thread
From: Stephen Boyd @ 2019-11-14 0:00 UTC (permalink / raw)
To: Zhou Yanjie, linux-mips
Cc: linux-kernel, linux-clk, devicetree, mturquette, paul.burton,
robh+dt, syq, mark.rutland, paul
Quoting Zhou Yanjie (2019-11-10 01:28:22)
> Add support for the clocks provided by the CGU in the Ingenic X1000
> SoC, making use of the cgu code to do the heavy lifting.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-11 1:13 ` Paul Cercueil
@ 2019-11-14 13:25 ` Zhou Yanjie
0 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-14 13:25 UTC (permalink / raw)
To: Paul Cercueil
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, sboyd, robh+dt, syq, mark.rutland
Hi Paul,
On 2019年11月11日 09:13, Paul Cercueil wrote:
> Hi Zhou,
>
>
> Le dim., nov. 10, 2019 at 17:28, Zhou Yanjie <zhouyanjie@zoho.com> a
> écrit :
>> Add the clock bindings for the X1000 Soc from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>
> Reviewed-by: Paul Cercueil <paul@crapouillou.net>
>
>> ---
>> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
>> include/dt-bindings/clock/x1000-cgu.h | 44
>> ++++++++++++++++++++++
>> 2 files changed, 45 insertions(+)
>> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>
> When you send a revised version of a patchset, it's common practice to
> have a per-patch changelog right here. Then a cover letter is only
> really needed for big patchsets that need extra information.
>
Thank you! I will pay attention to this next time.
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> index ba5a442..75598e6 100644
>> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt
>> @@ -11,6 +11,7 @@ Required properties:
>> * ingenic,jz4725b-cgu
>> * ingenic,jz4770-cgu
>> * ingenic,jz4780-cgu
>> + * ingenic,x1000-cgu
>> - reg : The address & length of the CGU registers.
>> - clocks : List of phandle & clock specifiers for clocks external to
>> the CGU.
>> Two such external clocks should be specified - first the external
>> crystal
>> diff --git a/include/dt-bindings/clock/x1000-cgu.h
>> b/include/dt-bindings/clock/x1000-cgu.h
>> new file mode 100644
>> index 00000000..bbaebaf
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/x1000-cgu.h
>> @@ -0,0 +1,44 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This header provides clock numbers for the ingenic,x1000-cgu DT
>> binding.
>> + *
>> + * They are roughly ordered as:
>> + * - external clocks
>> + * - PLLs
>> + * - muxes/dividers in the order they appear in the x1000
>> programmers manual
>> + * - gates in order of their bit in the CLKGR* registers
>> + */
>> +
>> +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
>> +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
>> +
>> +#define X1000_CLK_EXCLK 0
>> +#define X1000_CLK_RTCLK 1
>> +#define X1000_CLK_APLL 2
>> +#define X1000_CLK_MPLL 3
>> +#define X1000_CLK_SCLKA 4
>> +#define X1000_CLK_CPUMUX 5
>> +#define X1000_CLK_CPU 6
>> +#define X1000_CLK_L2CACHE 7
>> +#define X1000_CLK_AHB0 8
>> +#define X1000_CLK_AHB2PMUX 9
>> +#define X1000_CLK_AHB2 10
>> +#define X1000_CLK_PCLK 11
>> +#define X1000_CLK_DDR 12
>> +#define X1000_CLK_MAC 13
>> +#define X1000_CLK_MSCMUX 14
>> +#define X1000_CLK_MSC0 15
>> +#define X1000_CLK_MSC1 16
>> +#define X1000_CLK_SSIPLL 17
>> +#define X1000_CLK_SSIMUX 18
>> +#define X1000_CLK_SFC 19
>> +#define X1000_CLK_I2C0 20
>> +#define X1000_CLK_I2C1 21
>> +#define X1000_CLK_I2C2 22
>> +#define X1000_CLK_UART0 23
>> +#define X1000_CLK_UART1 24
>> +#define X1000_CLK_UART2 25
>> +#define X1000_CLK_SSI 26
>> +#define X1000_CLK_PDMA 27
>> +
>> +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
>> --
>> 2.7.4
>>
>>
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-12 0:55 ` Rob Herring
2019-11-13 23:59 ` Stephen Boyd
@ 2019-11-14 13:29 ` Zhou Yanjie
1 sibling, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-14 13:29 UTC (permalink / raw)
To: Rob Herring
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, sboyd, robh+dt, syq, mark.rutland, paul
Hi Rob,
On 2019年11月12日 08:55, Rob Herring wrote:
> On Sun, 10 Nov 2019 17:28:21 +0800, Zhou Yanjie wrote:
>> Add the clock bindings for the X1000 Soc from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
>> include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++
>> 2 files changed, 45 insertions(+)
>> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
I'm sorry, it's my mistake, I forgot to add these tags.
I'll pay more attention on this next time.
Best regards！
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings.
2019-11-13 23:59 ` Stephen Boyd
@ 2019-11-14 13:37 ` Zhou Yanjie
0 siblings, 0 replies; 22+ messages in thread
From: Zhou Yanjie @ 2019-11-14 13:37 UTC (permalink / raw)
To: Stephen Boyd, Rob Herring
Cc: linux-mips, linux-kernel, linux-clk, devicetree, mturquette,
paul.burton, robh+dt, syq, mark.rutland, paul
Hi Stephen,
On 2019年11月14日 07:59, Stephen Boyd wrote:
> Quoting Rob Herring (2019-11-11 16:55:44)
>> On Sun, 10 Nov 2019 17:28:21 +0800, Zhou Yanjie wrote:
>>> Add the clock bindings for the X1000 Soc from Ingenic.
>>>
>>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>>> ---
>>> .../devicetree/bindings/clock/ingenic,cgu.txt | 1 +
>>> include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++
>>> 2 files changed, 45 insertions(+)
>>> create mode 100644 include/dt-bindings/clock/x1000-cgu.h
>>>
>> Please add Acked-by/Reviewed-by tags when posting new versions. However,
>> there's no need to repost patches *only* to add the tags. The upstream
>> maintainer will do that for acks received on the version they apply.
>>
>> If a tag was not added on purpose, please state why and what changed.
> It looks like some extra defines were added. I carried forward your
> review tag.
>
I'm sorry that my mistake has caused you extra work,
I'll be careful to add tags next time.
Best regards!
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2019-11-14 13:37 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-18 17:50 clk: X1000: Add support for the X1000 Zhou Yanjie
2019-10-18 17:50 ` [PATCH 1/2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-10-18 17:50 ` [PATCH 2/2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
2019-10-21 12:31 ` Paul Cercueil
2019-10-22 15:34 ` Zhou Yanjie
2019-10-22 16:56 ` clk: X1000: Add support for the X1000 v2 Zhou Yanjie
2019-10-22 16:56 ` [PATCH 1/2 v2] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-10-25 21:49 ` Rob Herring
2019-10-22 16:56 ` [PATCH 2/2 v2] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
2019-11-02 21:27 ` Paul Cercueil
2019-11-10 9:28 ` clk: X1000: Add support for the X1000 v3 Zhou Yanjie
2019-11-10 9:28 ` [PATCH 1/2 v3] dt-bindings: clock: Add X1000 bindings Zhou Yanjie
2019-11-11 1:13 ` Paul Cercueil
2019-11-14 13:25 ` Zhou Yanjie
2019-11-12 0:55 ` Rob Herring
2019-11-13 23:59 ` Stephen Boyd
2019-11-14 13:37 ` Zhou Yanjie
2019-11-14 13:29 ` Zhou Yanjie
2019-11-14 0:00 ` Stephen Boyd
2019-11-10 9:28 ` [PATCH 2/2 v3] clk: Ingenic: Add CGU driver for X1000 Zhou Yanjie
2019-11-11 1:16 ` Paul Cercueil
2019-11-14 0:00 ` Stephen Boyd
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