From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 11/11] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
Date: Mon, 18 Nov 2019 19:45:12 +0300 [thread overview]
Message-ID: <20191118164512.8676-12-digetx@gmail.com> (raw)
In-Reply-To: <20191118164512.8676-1-digetx@gmail.com>
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30-beaver.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 6ebb3105af9e..86556622be25 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
@@ -2124,4 +2126,26 @@
<&tegra_car TEGRA30_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@2 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@3 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
};
--
2.23.0
prev parent reply other threads:[~2019-11-18 16:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 16:45 [PATCH v5 00/11] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 01/11] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 02/11] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 03/11] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 04/11] clk: tegra20: Use custom CCLK implementation Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 05/11] clk: tegra30: " Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 06/11] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 07/11] cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs Dmitry Osipenko
2019-11-18 16:51 ` Dmitry Osipenko
2019-12-13 13:27 ` Dmitry Osipenko
2019-12-16 4:05 ` Viresh Kumar
2019-12-16 4:08 ` Viresh Kumar
2019-12-16 14:11 ` Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 08/11] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 09/11] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-11-18 16:45 ` [PATCH v5 10/11] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-11-18 16:45 ` Dmitry Osipenko [this message]
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