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From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: mturquette@baylibre.com, sboyd@kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
	xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com,
	Elaine Zhang <zhangqing@rock-chips.com>
Subject: [PATCH v4 2/5] clk: rockchip: fix up the frac clk get rate error
Date: Wed,  4 Dec 2019 16:18:56 +0800	[thread overview]
Message-ID: <20191204081859.19454-3-zhangqing@rock-chips.com> (raw)
In-Reply-To: <20191204081859.19454-1-zhangqing@rock-chips.com>

support fractional divider with only one level parent clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
 	if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
 	    (fd->max_prate && fd->max_prate < p_rate)) {
 		p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
-		p_parent_rate = clk_hw_get_rate(p_parent);
-		*parent_rate = p_parent_rate;
-		if (fd->max_prate && p_parent_rate > fd->max_prate) {
-			div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
-			*parent_rate = p_parent_rate / div;
+		if (!p_parent) {
+			*parent_rate = p_rate;
+		} else {
+			p_parent_rate = clk_hw_get_rate(p_parent);
+			*parent_rate = p_parent_rate;
+			if (fd->max_prate && p_parent_rate > fd->max_prate) {
+				div = DIV_ROUND_UP(p_parent_rate,
+						   fd->max_prate);
+				*parent_rate = p_parent_rate / div;
+			}
 		}
 
 		if (*parent_rate < rate * 20) {
-			pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
-			       clk_hw_get_name(hw), *parent_rate, rate);
+			pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+				clk_hw_get_name(hw), *parent_rate, rate);
 			*m = 0;
 			*n = 1;
 			return;
-- 
2.17.1




  parent reply	other threads:[~2019-12-04  8:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-04  8:18 [PATCH v4 0/5] clk: rockchip: Support for some new features Elaine Zhang
2019-12-04  8:18 ` [PATCH v4 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider Elaine Zhang
2019-12-04  8:18 ` Elaine Zhang [this message]
2019-12-04  8:18 ` [PATCH v4 3/5] clk: rockchip: add a clock-type for muxes based in the pmugrf Elaine Zhang
2019-12-04  8:18 ` [PATCH v4 4/5] clk: rockchip: add pll up and down when change pll freq Elaine Zhang
2019-12-30 19:06   ` Stephen Boyd
2019-12-04  8:25 ` [PATCH v4 5/5] clk: rockchip: support pll setting by auto Elaine Zhang
2020-10-14  2:28 [PATCH v4 0/5] clk: rockchip: Support for some new features Elaine Zhang
2020-10-14  2:28 ` [PATCH v4 2/5] clk: rockchip: fix up the frac clk get rate error Elaine Zhang

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