* [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings @ 2019-12-05 7:26 Wen He 2019-12-05 7:26 ` [v11 2/2] clk: ls1028a: Add clock driver for Display output interface Wen He 2019-12-05 14:26 ` [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Rob Herring 0 siblings, 2 replies; 10+ messages in thread From: Wen He @ 2019-12-05 7:26 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Michael Walle, Li Yang, devicetree, linux-clk, linux-kernel Cc: Wen He LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display output interface. Add a YAML schema for this. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> --- change in v11: - renamed 'vco-frequency' to 'fsl,vco-hz' to clearly feild definiation .../devicetree/bindings/clock/fsl,plldig.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml new file mode 100644 index 000000000000..23cce65b3a93 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + fsl,vco-hz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-05 7:26 [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Wen He @ 2019-12-05 7:26 ` Wen He 2019-12-09 9:13 ` Wen He 2019-12-12 22:18 ` Stephen Boyd 2019-12-05 14:26 ` [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Rob Herring 1 sibling, 2 replies; 10+ messages in thread From: Wen He @ 2019-12-05 7:26 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Michael Walle, Li Yang, devicetree, linux-clk, linux-kernel Cc: Wen He Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable integer division and range of the display output pixel clock's 27-594MHz. Signed-off-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> --- drivers/clk/Kconfig | 10 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-plldig.c | 297 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/clk/clk-plldig.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 0530bebfc25a..9f6b0196c604 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,16 @@ config CLK_QORIQ This adds the clock driver support for Freescale QorIQ platforms using common clock framework. +config CLK_LS1028A_PLLDIG + tristate "Clock driver for LS1028A Display output" + depends on ARCH_LAYERSCAPE || COMPILE_TEST + default ARCH_LAYERSCAPE + help + This driver support the Display output interfaces(LCD, DPHY) pixel clocks + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all + features of the PLL are currently supported by the driver. By default, + configured bypass mode with this PLL. + config COMMON_CLK_XGENE bool "Clock driver for APM XGene SoC" default ARCH_XGENE diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0138fb14e6f8..97d1e5bc6de5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o +obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new file mode 100644 index 000000000000..1942686f0254 --- /dev/null +++ b/drivers/clk/clk-plldig.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + * Clock driver for LS1028A Display output interfaces(LCD, DPHY). + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/bitfield.h> + +/* PLLDIG register offsets and bit masks */ +#define PLLDIG_REG_PLLSR 0x24 +#define PLLDIG_LOCK_MASK BIT(2) +#define PLLDIG_REG_PLLDV 0x28 +#define PLLDIG_MFD_MASK GENMASK(7, 0) +#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25) +#define PLLDIG_REG_PLLFM 0x2c +#define PLLDIG_SSCGBYP_ENABLE BIT(30) +#define PLLDIG_REG_PLLFD 0x30 +#define PLLDIG_FDEN BIT(30) +#define PLLDIG_FRAC_MASK GENMASK(15, 0) +#define PLLDIG_REG_PLLCAL1 0x38 +#define PLLDIG_REG_PLLCAL2 0x3c + +/* Range of the VCO frequencies, in Hz */ +#define PLLDIG_MIN_VCO_FREQ 650000000 +#define PLLDIG_MAX_VCO_FREQ 1300000000 + +/* Range of the output frequencies, in Hz */ +#define PHI1_MIN_FREQ 27000000 +#define PHI1_MAX_FREQ 600000000 + +/* Maximum value of the reduced frequency divider */ +#define MAX_RFDPHI1 63UL + +/* Best value of multiplication factor divider */ +#define PLLDIG_DEFAULT_MFD 44 + +/* + * Denominator part of the fractional part of the + * loop multiplication factor. + */ +#define MFDEN 20480 + +static const struct clk_parent_data parent_data[] = { + {.index = 0}, +}; + +struct clk_plldig { + struct clk_hw hw; + void __iomem *regs; + unsigned int vco_freq; +}; + +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) + +static int plldig_enable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + PLLDIG_REG_PLLFM); + /* + * Use Bypass mode with PLL off by default, the frequency overshoot + * detector output was disable. SSCG Bypass mode should be enable. + */ + val |= PLLDIG_SSCGBYP_ENABLE; + writel(val, data->regs + PLLDIG_REG_PLLFM); + + return 0; +} + +static void plldig_disable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + PLLDIG_REG_PLLFM); + + val &= ~PLLDIG_SSCGBYP_ENABLE; + val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0); + + writel(val, data->regs + PLLDIG_REG_PLLFM); +} + +static int plldig_is_enabled(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + + return (readl(data->regs + PLLDIG_REG_PLLFM) & + PLLDIG_SSCGBYP_ENABLE); +} + +static unsigned long plldig_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val, rfdphi1; + + val = readl(data->regs + PLLDIG_REG_PLLDV); + + /* Check if PLL is bypassed */ + if (val & PLLDIG_SSCGBYP_ENABLE) + return parent_rate; + + rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val); + + /* + * If RFDPHI1 has a value of 1 the VCO frequency is also divided by + * one. + */ + if (!rfdphi1) + rfdphi1 = 1; + + return DIV_ROUND_UP(data->vco_freq, rfdphi1); +} + +static unsigned long plldig_calc_target_div(unsigned long vco_freq, + unsigned long target_rate) +{ + unsigned long div; + + div = DIV_ROUND_CLOSEST(vco_freq, target_rate); + div = max(1UL, div); + div = min(div, MAX_RFDPHI1); + + return div; +} + +static int plldig_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int div; + + if (req->rate < PHI1_MIN_FREQ) + req->rate = PHI1_MIN_FREQ; + if (req->rate > PHI1_MAX_FREQ) + req->rate = PHI1_MAX_FREQ; + + div = plldig_calc_target_div(data->vco_freq, req->rate); + req->rate = DIV_ROUND_UP(data->vco_freq, div); + + return 0; +} + +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int val, cond; + unsigned int rfdphi1; + + if (rate < PHI1_MIN_FREQ) + rate = PHI1_MIN_FREQ; + if (rate > PHI1_MAX_FREQ) + rate = PHI1_MAX_FREQ; + + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); + + /* update the divider value */ + val = readl(data->regs + PLLDIG_REG_PLLDV); + val &= ~PLLDIG_RFDPHI1_MASK; + val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1); + writel(val, data->regs + PLLDIG_REG_PLLDV); + + /* delay 200us make sure that old lock state is cleared */ + udelay(200); + + /* Wait until PLL is locked or timeout (maximum 1000 usecs) */ + return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond, + cond & PLLDIG_LOCK_MASK, 0, + USEC_PER_MSEC); +} + +static const struct clk_ops plldig_clk_ops = { + .enable = plldig_enable, + .disable = plldig_disable, + .is_enabled = plldig_is_enabled, + .recalc_rate = plldig_recalc_rate, + .determine_rate = plldig_determine_rate, + .set_rate = plldig_set_rate, +}; + +static int plldig_init(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long val; + unsigned long long lltmp; + unsigned int mfd, fracdiv = 0; + + if (!parent) + return -EINVAL; + + if (data->vco_freq) { + mfd = data->vco_freq / parent_rate; + lltmp = data->vco_freq % parent_rate; + lltmp *= MFDEN; + do_div(lltmp, parent_rate); + fracdiv = lltmp; + } else { + mfd = PLLDIG_DEFAULT_MFD; + data->vco_freq = parent_rate * mfd; + } + + val = FIELD_PREP(PLLDIG_MFD_MASK, mfd); + writel(val, data->regs + PLLDIG_REG_PLLDV); + + if (fracdiv) { + val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv); + /* Enable fractional divider */ + val |= PLLDIG_FDEN; + writel(val, data->regs + PLLDIG_REG_PLLFD); + } + + return 0; +} + +static int plldig_clk_probe(struct platform_device *pdev) +{ + struct clk_plldig *data; + struct resource *mem; + struct device *dev = &pdev->dev; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(dev, mem); + if (IS_ERR(data->regs)) + return PTR_ERR(data->regs); + + data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk", + parent_data, + &plldig_clk_ops, + 0); + + ret = devm_clk_hw_register(dev, &data->hw); + if (ret) { + dev_err(dev, "failed to register %s clock\n", + dev->of_node->name); + return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &data->hw); + if (ret) { + dev_err(dev, "unable to add clk provider\n"); + return ret; + } + + /* + * The frequency of the VCO cannot be changed during runtime. + * Therefore, let the user specify a desired frequency. + */ + if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", + &data->vco_freq)) { + if (data->vco_freq < PLLDIG_MIN_VCO_FREQ || + data->vco_freq > PLLDIG_MAX_VCO_FREQ) + return -EINVAL; + } + + return plldig_init(&data->hw); +} + +static const struct of_device_id plldig_clk_id[] = { + { .compatible = "fsl,ls1028a-plldig"}, + { } +}; +MODULE_DEVICE_TABLE(of, plldig_clk_id); + +static struct platform_driver plldig_clk_driver = { + .driver = { + .name = "plldig-clock", + .of_match_table = plldig_clk_id, + }, + .probe = plldig_clk_probe, +}; +module_platform_driver(plldig_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>"); +MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-05 7:26 ` [v11 2/2] clk: ls1028a: Add clock driver for Display output interface Wen He @ 2019-12-09 9:13 ` Wen He 2019-12-12 22:18 ` Stephen Boyd 1 sibling, 0 replies; 10+ messages in thread From: Wen He @ 2019-12-09 9:13 UTC (permalink / raw) To: Wen He, Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland, Michael Walle, Leo Li, devicetree, linux-clk, linux-kernel > -----Original Message----- > From: Wen He <wen.he_1@nxp.com> > Sent: 2019年12月5日 15:27 > To: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark Rutland > <mark.rutland@arm.com>; Michael Walle <michael@walle.cc>; Leo Li > <leoyang.li@nxp.com>; devicetree@vger.kernel.org; linux-clk@vger.kernel.org; > linux-kernel@vger.kernel.org > Cc: Wen He <wen.he_1@nxp.com> > Subject: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface > Hi Maintainer, Do you have any comments for this patch? Best Regards, Wen > Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), as > implemented in TSMC CLN28HPM PLL, this PLL supports the programmable > integer division and range of the display output pixel clock's 27-594MHz. > > Signed-off-by: Wen He <wen.he_1@nxp.com> > Signed-off-by: Michael Walle <michael@walle.cc> > --- > drivers/clk/Kconfig | 10 ++ > drivers/clk/Makefile | 1 + > drivers/clk/clk-plldig.c | 297 > +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 308 insertions(+) > create mode 100644 drivers/clk/clk-plldig.c > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index > 0530bebfc25a..9f6b0196c604 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -218,6 +218,16 @@ config CLK_QORIQ > This adds the clock driver support for Freescale QorIQ platforms > using common clock framework. > > +config CLK_LS1028A_PLLDIG > + tristate "Clock driver for LS1028A Display output" > + depends on ARCH_LAYERSCAPE || COMPILE_TEST > + default ARCH_LAYERSCAPE > + help > + This driver support the Display output interfaces(LCD, DPHY) pixel > clocks > + of the QorIQ Layerscape LS1028A, as implemented TSMC > CLN28HPM PLL. Not all > + features of the PLL are currently supported by the driver. By > default, > + configured bypass mode with this PLL. > + > config COMMON_CLK_XGENE > bool "Clock driver for APM XGene SoC" > default ARCH_XGENE > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > 0138fb14e6f8..97d1e5bc6de5 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile > @@ -43,6 +43,7 @@ obj-$(CONFIG_ARCH_NPCM7XX) += > clk-npcm7xx.o > obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o > obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o > obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o > +obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o > obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o > obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o > obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o > diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c new file mode > 100644 index 000000000000..1942686f0254 > --- /dev/null > +++ b/drivers/clk/clk-plldig.c > @@ -0,0 +1,297 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2019 NXP > + * > + * Clock driver for LS1028A Display output interfaces(LCD, DPHY). > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/module.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/bitfield.h> > + > +/* PLLDIG register offsets and bit masks */ > +#define PLLDIG_REG_PLLSR 0x24 > +#define PLLDIG_LOCK_MASK BIT(2) > +#define PLLDIG_REG_PLLDV 0x28 > +#define PLLDIG_MFD_MASK GENMASK(7, 0) > +#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25) > +#define PLLDIG_REG_PLLFM 0x2c > +#define PLLDIG_SSCGBYP_ENABLE BIT(30) > +#define PLLDIG_REG_PLLFD 0x30 > +#define PLLDIG_FDEN BIT(30) > +#define PLLDIG_FRAC_MASK GENMASK(15, 0) > +#define PLLDIG_REG_PLLCAL1 0x38 > +#define PLLDIG_REG_PLLCAL2 0x3c > + > +/* Range of the VCO frequencies, in Hz */ > +#define PLLDIG_MIN_VCO_FREQ 650000000 > +#define PLLDIG_MAX_VCO_FREQ 1300000000 > + > +/* Range of the output frequencies, in Hz */ > +#define PHI1_MIN_FREQ 27000000 > +#define PHI1_MAX_FREQ 600000000 > + > +/* Maximum value of the reduced frequency divider */ > +#define MAX_RFDPHI1 63UL > + > +/* Best value of multiplication factor divider */ > +#define PLLDIG_DEFAULT_MFD 44 > + > +/* > + * Denominator part of the fractional part of the > + * loop multiplication factor. > + */ > +#define MFDEN 20480 > + > +static const struct clk_parent_data parent_data[] = { > + {.index = 0}, > +}; > + > +struct clk_plldig { > + struct clk_hw hw; > + void __iomem *regs; > + unsigned int vco_freq; > +}; > + > +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) > + > +static int plldig_enable(struct clk_hw *hw) { > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val; > + > + val = readl(data->regs + PLLDIG_REG_PLLFM); > + /* > + * Use Bypass mode with PLL off by default, the frequency overshoot > + * detector output was disable. SSCG Bypass mode should be enable. > + */ > + val |= PLLDIG_SSCGBYP_ENABLE; > + writel(val, data->regs + PLLDIG_REG_PLLFM); > + > + return 0; > +} > + > +static void plldig_disable(struct clk_hw *hw) { > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val; > + > + val = readl(data->regs + PLLDIG_REG_PLLFM); > + > + val &= ~PLLDIG_SSCGBYP_ENABLE; > + val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0); > + > + writel(val, data->regs + PLLDIG_REG_PLLFM); } > + > +static int plldig_is_enabled(struct clk_hw *hw) { > + struct clk_plldig *data = to_clk_plldig(hw); > + > + return (readl(data->regs + PLLDIG_REG_PLLFM) & > + PLLDIG_SSCGBYP_ENABLE); > +} > + > +static unsigned long plldig_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val, rfdphi1; > + > + val = readl(data->regs + PLLDIG_REG_PLLDV); > + > + /* Check if PLL is bypassed */ > + if (val & PLLDIG_SSCGBYP_ENABLE) > + return parent_rate; > + > + rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val); > + > + /* > + * If RFDPHI1 has a value of 1 the VCO frequency is also divided by > + * one. > + */ > + if (!rfdphi1) > + rfdphi1 = 1; > + > + return DIV_ROUND_UP(data->vco_freq, rfdphi1); } > + > +static unsigned long plldig_calc_target_div(unsigned long vco_freq, > + unsigned long target_rate) > +{ > + unsigned long div; > + > + div = DIV_ROUND_CLOSEST(vco_freq, target_rate); > + div = max(1UL, div); > + div = min(div, MAX_RFDPHI1); > + > + return div; > +} > + > +static int plldig_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + unsigned int div; > + > + if (req->rate < PHI1_MIN_FREQ) > + req->rate = PHI1_MIN_FREQ; > + if (req->rate > PHI1_MAX_FREQ) > + req->rate = PHI1_MAX_FREQ; > + > + div = plldig_calc_target_div(data->vco_freq, req->rate); > + req->rate = DIV_ROUND_UP(data->vco_freq, div); > + > + return 0; > +} > + > +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + unsigned int val, cond; > + unsigned int rfdphi1; > + > + if (rate < PHI1_MIN_FREQ) > + rate = PHI1_MIN_FREQ; > + if (rate > PHI1_MAX_FREQ) > + rate = PHI1_MAX_FREQ; > + > + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); > + > + /* update the divider value */ > + val = readl(data->regs + PLLDIG_REG_PLLDV); > + val &= ~PLLDIG_RFDPHI1_MASK; > + val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1); > + writel(val, data->regs + PLLDIG_REG_PLLDV); > + > + /* delay 200us make sure that old lock state is cleared */ > + udelay(200); > + > + /* Wait until PLL is locked or timeout (maximum 1000 usecs) */ > + return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond, > + cond & PLLDIG_LOCK_MASK, 0, > + USEC_PER_MSEC); > +} > + > +static const struct clk_ops plldig_clk_ops = { > + .enable = plldig_enable, > + .disable = plldig_disable, > + .is_enabled = plldig_is_enabled, > + .recalc_rate = plldig_recalc_rate, > + .determine_rate = plldig_determine_rate, > + .set_rate = plldig_set_rate, > +}; > + > +static int plldig_init(struct clk_hw *hw) { > + struct clk_plldig *data = to_clk_plldig(hw); > + struct clk_hw *parent = clk_hw_get_parent(hw); > + unsigned long parent_rate = clk_hw_get_rate(parent); > + unsigned long val; > + unsigned long long lltmp; > + unsigned int mfd, fracdiv = 0; > + > + if (!parent) > + return -EINVAL; > + > + if (data->vco_freq) { > + mfd = data->vco_freq / parent_rate; > + lltmp = data->vco_freq % parent_rate; > + lltmp *= MFDEN; > + do_div(lltmp, parent_rate); > + fracdiv = lltmp; > + } else { > + mfd = PLLDIG_DEFAULT_MFD; > + data->vco_freq = parent_rate * mfd; > + } > + > + val = FIELD_PREP(PLLDIG_MFD_MASK, mfd); > + writel(val, data->regs + PLLDIG_REG_PLLDV); > + > + if (fracdiv) { > + val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv); > + /* Enable fractional divider */ > + val |= PLLDIG_FDEN; > + writel(val, data->regs + PLLDIG_REG_PLLFD); > + } > + > + return 0; > +} > + > +static int plldig_clk_probe(struct platform_device *pdev) { > + struct clk_plldig *data; > + struct resource *mem; > + struct device *dev = &pdev->dev; > + int ret; > + > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs = devm_ioremap_resource(dev, mem); > + if (IS_ERR(data->regs)) > + return PTR_ERR(data->regs); > + > + data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk", > + parent_data, > + &plldig_clk_ops, > + 0); > + > + ret = devm_clk_hw_register(dev, &data->hw); > + if (ret) { > + dev_err(dev, "failed to register %s clock\n", > + dev->of_node->name); > + return ret; > + } > + > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, > + &data->hw); > + if (ret) { > + dev_err(dev, "unable to add clk provider\n"); > + return ret; > + } > + > + /* > + * The frequency of the VCO cannot be changed during runtime. > + * Therefore, let the user specify a desired frequency. > + */ > + if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", > + &data->vco_freq)) { > + if (data->vco_freq < PLLDIG_MIN_VCO_FREQ || > + data->vco_freq > PLLDIG_MAX_VCO_FREQ) > + return -EINVAL; > + } > + > + return plldig_init(&data->hw); > +} > + > +static const struct of_device_id plldig_clk_id[] = { > + { .compatible = "fsl,ls1028a-plldig"}, > + { } > +}; > +MODULE_DEVICE_TABLE(of, plldig_clk_id); > + > +static struct platform_driver plldig_clk_driver = { > + .driver = { > + .name = "plldig-clock", > + .of_match_table = plldig_clk_id, > + }, > + .probe = plldig_clk_probe, > +}; > +module_platform_driver(plldig_clk_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>"); > MODULE_DESCRIPTION("LS1028A > +Display output interface pixel clock driver"); > -- > 2.17.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-05 7:26 ` [v11 2/2] clk: ls1028a: Add clock driver for Display output interface Wen He 2019-12-09 9:13 ` Wen He @ 2019-12-12 22:18 ` Stephen Boyd 2019-12-13 0:06 ` Michael Walle 1 sibling, 1 reply; 10+ messages in thread From: Stephen Boyd @ 2019-12-12 22:18 UTC (permalink / raw) To: Li Yang, Mark Rutland, Michael Turquette, Michael Walle, Rob Herring, Wen He, devicetree, linux-clk, linux-kernel Cc: Wen He Quoting Wen He (2019-12-04 23:26:53) > Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY), > as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable > integer division and range of the display output pixel clock's 27-594MHz. > > Signed-off-by: Wen He <wen.he_1@nxp.com> > Signed-off-by: Michael Walle <michael@walle.cc> Is Michael the author? SoB chain is backwards here. > diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c > new file mode 100644 > index 000000000000..1942686f0254 > --- /dev/null > +++ b/drivers/clk/clk-plldig.c > @@ -0,0 +1,297 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2019 NXP > + * > + * Clock driver for LS1028A Display output interfaces(LCD, DPHY). > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/device.h> > +#include <linux/module.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/iopoll.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/bitfield.h> > + > +/* PLLDIG register offsets and bit masks */ > +#define PLLDIG_REG_PLLSR 0x24 > +#define PLLDIG_LOCK_MASK BIT(2) > +#define PLLDIG_REG_PLLDV 0x28 > +#define PLLDIG_MFD_MASK GENMASK(7, 0) > +#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25) > +#define PLLDIG_REG_PLLFM 0x2c > +#define PLLDIG_SSCGBYP_ENABLE BIT(30) > +#define PLLDIG_REG_PLLFD 0x30 > +#define PLLDIG_FDEN BIT(30) > +#define PLLDIG_FRAC_MASK GENMASK(15, 0) > +#define PLLDIG_REG_PLLCAL1 0x38 > +#define PLLDIG_REG_PLLCAL2 0x3c > + > +/* Range of the VCO frequencies, in Hz */ > +#define PLLDIG_MIN_VCO_FREQ 650000000 > +#define PLLDIG_MAX_VCO_FREQ 1300000000 > + > +/* Range of the output frequencies, in Hz */ > +#define PHI1_MIN_FREQ 27000000 > +#define PHI1_MAX_FREQ 600000000 > + > +/* Maximum value of the reduced frequency divider */ > +#define MAX_RFDPHI1 63UL > + > +/* Best value of multiplication factor divider */ > +#define PLLDIG_DEFAULT_MFD 44 > + > +/* > + * Denominator part of the fractional part of the > + * loop multiplication factor. > + */ > +#define MFDEN 20480 > + > +static const struct clk_parent_data parent_data[] = { > + {.index = 0}, Nitpick: Add spaces after { and before } > +}; > + > +struct clk_plldig { > + struct clk_hw hw; > + void __iomem *regs; > + unsigned int vco_freq; > +}; > + > +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) > + > +static int plldig_enable(struct clk_hw *hw) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val; > + > + val = readl(data->regs + PLLDIG_REG_PLLFM); > + /* > + * Use Bypass mode with PLL off by default, the frequency overshoot > + * detector output was disable. SSCG Bypass mode should be enable. > + */ > + val |= PLLDIG_SSCGBYP_ENABLE; > + writel(val, data->regs + PLLDIG_REG_PLLFM); > + > + return 0; > +} > + > +static void plldig_disable(struct clk_hw *hw) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val; > + > + val = readl(data->regs + PLLDIG_REG_PLLFM); > + > + val &= ~PLLDIG_SSCGBYP_ENABLE; > + val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0); > + > + writel(val, data->regs + PLLDIG_REG_PLLFM); > +} > + > +static int plldig_is_enabled(struct clk_hw *hw) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + > + return (readl(data->regs + PLLDIG_REG_PLLFM) & Please drop useless parenthesis. > + PLLDIG_SSCGBYP_ENABLE); > +} > + > +static unsigned long plldig_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + u32 val, rfdphi1; > + > + val = readl(data->regs + PLLDIG_REG_PLLDV); > + > + /* Check if PLL is bypassed */ > + if (val & PLLDIG_SSCGBYP_ENABLE) > + return parent_rate; > + > + rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val); > + > + /* > + * If RFDPHI1 has a value of 1 the VCO frequency is also divided by > + * one. > + */ > + if (!rfdphi1) > + rfdphi1 = 1; > + > + return DIV_ROUND_UP(data->vco_freq, rfdphi1); > +} > + > +static unsigned long plldig_calc_target_div(unsigned long vco_freq, > + unsigned long target_rate) > +{ > + unsigned long div; > + > + div = DIV_ROUND_CLOSEST(vco_freq, target_rate); > + div = max(1UL, div); > + div = min(div, MAX_RFDPHI1); Use clamp(). > + > + return div; > +} > + > +static int plldig_determine_rate(struct clk_hw *hw, > + struct clk_rate_request *req) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + unsigned int div; > + > + if (req->rate < PHI1_MIN_FREQ) > + req->rate = PHI1_MIN_FREQ; > + if (req->rate > PHI1_MAX_FREQ) > + req->rate = PHI1_MAX_FREQ; Use clamp() > + > + div = plldig_calc_target_div(data->vco_freq, req->rate); > + req->rate = DIV_ROUND_UP(data->vco_freq, div); > + > + return 0; > +} > + > +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + unsigned int val, cond; > + unsigned int rfdphi1; > + > + if (rate < PHI1_MIN_FREQ) > + rate = PHI1_MIN_FREQ; > + if (rate > PHI1_MAX_FREQ) > + rate = PHI1_MAX_FREQ; Use clamp() > + > + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); > + > + /* update the divider value */ > + val = readl(data->regs + PLLDIG_REG_PLLDV); > + val &= ~PLLDIG_RFDPHI1_MASK; > + val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1); > + writel(val, data->regs + PLLDIG_REG_PLLDV); > + > + /* delay 200us make sure that old lock state is cleared */ > + udelay(200); Please remove 'delay 200us' from the comment. Just say that we're waiting for old lock state to clear. It's clear from the code how much time it is. > + > + /* Wait until PLL is locked or timeout (maximum 1000 usecs) */ Drop the time. It's a millisecond. > + return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond, > + cond & PLLDIG_LOCK_MASK, 0, > + USEC_PER_MSEC); > +} > + > +static const struct clk_ops plldig_clk_ops = { > + .enable = plldig_enable, > + .disable = plldig_disable, > + .is_enabled = plldig_is_enabled, > + .recalc_rate = plldig_recalc_rate, > + .determine_rate = plldig_determine_rate, > + .set_rate = plldig_set_rate, > +}; > + > +static int plldig_init(struct clk_hw *hw) > +{ > + struct clk_plldig *data = to_clk_plldig(hw); > + struct clk_hw *parent = clk_hw_get_parent(hw); > + unsigned long parent_rate = clk_hw_get_rate(parent); > + unsigned long val; > + unsigned long long lltmp; > + unsigned int mfd, fracdiv = 0; > + > + if (!parent) > + return -EINVAL; > + > + if (data->vco_freq) { > + mfd = data->vco_freq / parent_rate; > + lltmp = data->vco_freq % parent_rate; > + lltmp *= MFDEN; > + do_div(lltmp, parent_rate); > + fracdiv = lltmp; > + } else { > + mfd = PLLDIG_DEFAULT_MFD; > + data->vco_freq = parent_rate * mfd; > + } > + > + val = FIELD_PREP(PLLDIG_MFD_MASK, mfd); > + writel(val, data->regs + PLLDIG_REG_PLLDV); > + > + if (fracdiv) { > + val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv); > + /* Enable fractional divider */ Remove useless comment please. Or move above the if condition. > + val |= PLLDIG_FDEN; > + writel(val, data->regs + PLLDIG_REG_PLLFD); > + } > + > + return 0; > +} > + > +static int plldig_clk_probe(struct platform_device *pdev) > +{ > + struct clk_plldig *data; > + struct resource *mem; > + struct device *dev = &pdev->dev; > + int ret; > + > + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs = devm_ioremap_resource(dev, mem); We have devm_platform_ioremap_resource() for this now. > + if (IS_ERR(data->regs)) > + return PTR_ERR(data->regs); > + > + data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk", > + parent_data, > + &plldig_clk_ops, > + 0); > + > + ret = devm_clk_hw_register(dev, &data->hw); > + if (ret) { > + dev_err(dev, "failed to register %s clock\n", > + dev->of_node->name); > + return ret; > + } > + > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, > + &data->hw); > + if (ret) { > + dev_err(dev, "unable to add clk provider\n"); > + return ret; > + } > + > + /* > + * The frequency of the VCO cannot be changed during runtime. > + * Therefore, let the user specify a desired frequency. > + */ > + if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", > + &data->vco_freq)) { > + if (data->vco_freq < PLLDIG_MIN_VCO_FREQ || > + data->vco_freq > PLLDIG_MAX_VCO_FREQ) > + return -EINVAL; > + } > + > + return plldig_init(&data->hw); > +} > + > +static const struct of_device_id plldig_clk_id[] = { > + { .compatible = "fsl,ls1028a-plldig"}, Nitpick: Add a space before } > + { } > +}; > +MODULE_DEVICE_TABLE(of, plldig_clk_id); > + ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-12 22:18 ` Stephen Boyd @ 2019-12-13 0:06 ` Michael Walle 2019-12-16 17:55 ` Stephen Boyd 0 siblings, 1 reply; 10+ messages in thread From: Michael Walle @ 2019-12-13 0:06 UTC (permalink / raw) To: Stephen Boyd, Li Yang, Mark Rutland, Michael Turquette, Rob Herring, Wen He, devicetree, linux-clk, linux-kernel Am 12. Dezember 2019 23:18:16 MEZ schrieb Stephen Boyd <sboyd@kernel.org>: >Quoting Wen He (2019-12-04 23:26:53) >> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, >DPHY), >> as implemented in TSMC CLN28HPM PLL, this PLL supports the >programmable >> integer division and range of the display output pixel clock's >27-594MHz. >> >> Signed-off-by: Wen He <wen.he_1@nxp.com> >> Signed-off-by: Michael Walle <michael@walle.cc> > >Is Michael the author? SoB chain is backwards here. the original driver was from Wen. I've just supplied some code and the vco frequency stuff. so its basically a sob of us both. -michael > >> diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c >> new file mode 100644 >> index 000000000000..1942686f0254 >> --- /dev/null >> +++ b/drivers/clk/clk-plldig.c >> @@ -0,0 +1,297 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright 2019 NXP >> + * >> + * Clock driver for LS1028A Display output interfaces(LCD, DPHY). >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/device.h> >> +#include <linux/module.h> >> +#include <linux/err.h> >> +#include <linux/io.h> >> +#include <linux/iopoll.h> >> +#include <linux/of.h> >> +#include <linux/of_address.h> >> +#include <linux/of_device.h> >> +#include <linux/platform_device.h> >> +#include <linux/slab.h> >> +#include <linux/bitfield.h> >> + >> +/* PLLDIG register offsets and bit masks */ >> +#define PLLDIG_REG_PLLSR 0x24 >> +#define PLLDIG_LOCK_MASK BIT(2) >> +#define PLLDIG_REG_PLLDV 0x28 >> +#define PLLDIG_MFD_MASK GENMASK(7, 0) >> +#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25) >> +#define PLLDIG_REG_PLLFM 0x2c >> +#define PLLDIG_SSCGBYP_ENABLE BIT(30) >> +#define PLLDIG_REG_PLLFD 0x30 >> +#define PLLDIG_FDEN BIT(30) >> +#define PLLDIG_FRAC_MASK GENMASK(15, 0) >> +#define PLLDIG_REG_PLLCAL1 0x38 >> +#define PLLDIG_REG_PLLCAL2 0x3c >> + >> +/* Range of the VCO frequencies, in Hz */ >> +#define PLLDIG_MIN_VCO_FREQ 650000000 >> +#define PLLDIG_MAX_VCO_FREQ 1300000000 >> + >> +/* Range of the output frequencies, in Hz */ >> +#define PHI1_MIN_FREQ 27000000 >> +#define PHI1_MAX_FREQ 600000000 >> + >> +/* Maximum value of the reduced frequency divider */ >> +#define MAX_RFDPHI1 63UL >> + >> +/* Best value of multiplication factor divider */ >> +#define PLLDIG_DEFAULT_MFD 44 >> + >> +/* >> + * Denominator part of the fractional part of the >> + * loop multiplication factor. >> + */ >> +#define MFDEN 20480 >> + >> +static const struct clk_parent_data parent_data[] = { >> + {.index = 0}, > >Nitpick: Add spaces after { and before } > >> +}; >> + >> +struct clk_plldig { >> + struct clk_hw hw; >> + void __iomem *regs; >> + unsigned int vco_freq; >> +}; >> + >> +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, >hw) >> + >> +static int plldig_enable(struct clk_hw *hw) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + u32 val; >> + >> + val = readl(data->regs + PLLDIG_REG_PLLFM); >> + /* >> + * Use Bypass mode with PLL off by default, the frequency >overshoot >> + * detector output was disable. SSCG Bypass mode should be >enable. >> + */ >> + val |= PLLDIG_SSCGBYP_ENABLE; >> + writel(val, data->regs + PLLDIG_REG_PLLFM); >> + >> + return 0; >> +} >> + >> +static void plldig_disable(struct clk_hw *hw) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + u32 val; >> + >> + val = readl(data->regs + PLLDIG_REG_PLLFM); >> + >> + val &= ~PLLDIG_SSCGBYP_ENABLE; >> + val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0); >> + >> + writel(val, data->regs + PLLDIG_REG_PLLFM); >> +} >> + >> +static int plldig_is_enabled(struct clk_hw *hw) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + >> + return (readl(data->regs + PLLDIG_REG_PLLFM) & > >Please drop useless parenthesis. > >> + PLLDIG_SSCGBYP_ENABLE); >> +} >> + >> +static unsigned long plldig_recalc_rate(struct clk_hw *hw, >> + unsigned long parent_rate) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + u32 val, rfdphi1; >> + >> + val = readl(data->regs + PLLDIG_REG_PLLDV); >> + >> + /* Check if PLL is bypassed */ >> + if (val & PLLDIG_SSCGBYP_ENABLE) >> + return parent_rate; >> + >> + rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val); >> + >> + /* >> + * If RFDPHI1 has a value of 1 the VCO frequency is also >divided by >> + * one. >> + */ >> + if (!rfdphi1) >> + rfdphi1 = 1; >> + >> + return DIV_ROUND_UP(data->vco_freq, rfdphi1); >> +} >> + >> +static unsigned long plldig_calc_target_div(unsigned long vco_freq, >> + unsigned long >target_rate) >> +{ >> + unsigned long div; >> + >> + div = DIV_ROUND_CLOSEST(vco_freq, target_rate); >> + div = max(1UL, div); >> + div = min(div, MAX_RFDPHI1); > >Use clamp(). > >> + >> + return div; >> +} >> + >> +static int plldig_determine_rate(struct clk_hw *hw, >> + struct clk_rate_request *req) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + unsigned int div; >> + >> + if (req->rate < PHI1_MIN_FREQ) >> + req->rate = PHI1_MIN_FREQ; >> + if (req->rate > PHI1_MAX_FREQ) >> + req->rate = PHI1_MAX_FREQ; > >Use clamp() > >> + >> + div = plldig_calc_target_div(data->vco_freq, req->rate); >> + req->rate = DIV_ROUND_UP(data->vco_freq, div); >> + >> + return 0; >> +} >> + >> +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, >> + unsigned long parent_rate) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + unsigned int val, cond; >> + unsigned int rfdphi1; >> + >> + if (rate < PHI1_MIN_FREQ) >> + rate = PHI1_MIN_FREQ; >> + if (rate > PHI1_MAX_FREQ) >> + rate = PHI1_MAX_FREQ; > >Use clamp() > >> + >> + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); >> + >> + /* update the divider value */ >> + val = readl(data->regs + PLLDIG_REG_PLLDV); >> + val &= ~PLLDIG_RFDPHI1_MASK; >> + val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1); >> + writel(val, data->regs + PLLDIG_REG_PLLDV); >> + >> + /* delay 200us make sure that old lock state is cleared */ >> + udelay(200); > >Please remove 'delay 200us' from the comment. Just say that we're >waiting >for old lock state to clear. It's clear from the code how much time it >is. > >> + >> + /* Wait until PLL is locked or timeout (maximum 1000 usecs) >*/ > >Drop the time. It's a millisecond. > >> + return readl_poll_timeout_atomic(data->regs + >PLLDIG_REG_PLLSR, cond, >> + cond & PLLDIG_LOCK_MASK, 0, >> + USEC_PER_MSEC); >> +} >> + >> +static const struct clk_ops plldig_clk_ops = { >> + .enable = plldig_enable, >> + .disable = plldig_disable, >> + .is_enabled = plldig_is_enabled, >> + .recalc_rate = plldig_recalc_rate, >> + .determine_rate = plldig_determine_rate, >> + .set_rate = plldig_set_rate, >> +}; >> + >> +static int plldig_init(struct clk_hw *hw) >> +{ >> + struct clk_plldig *data = to_clk_plldig(hw); >> + struct clk_hw *parent = clk_hw_get_parent(hw); >> + unsigned long parent_rate = clk_hw_get_rate(parent); >> + unsigned long val; >> + unsigned long long lltmp; >> + unsigned int mfd, fracdiv = 0; >> + >> + if (!parent) >> + return -EINVAL; >> + >> + if (data->vco_freq) { >> + mfd = data->vco_freq / parent_rate; >> + lltmp = data->vco_freq % parent_rate; >> + lltmp *= MFDEN; >> + do_div(lltmp, parent_rate); >> + fracdiv = lltmp; >> + } else { >> + mfd = PLLDIG_DEFAULT_MFD; >> + data->vco_freq = parent_rate * mfd; >> + } >> + >> + val = FIELD_PREP(PLLDIG_MFD_MASK, mfd); >> + writel(val, data->regs + PLLDIG_REG_PLLDV); >> + >> + if (fracdiv) { >> + val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv); >> + /* Enable fractional divider */ > >Remove useless comment please. Or move above the if condition. > >> + val |= PLLDIG_FDEN; >> + writel(val, data->regs + PLLDIG_REG_PLLFD); >> + } >> + >> + return 0; >> +} >> + >> +static int plldig_clk_probe(struct platform_device *pdev) >> +{ >> + struct clk_plldig *data; >> + struct resource *mem; >> + struct device *dev = &pdev->dev; >> + int ret; >> + >> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); >> + if (!data) >> + return -ENOMEM; >> + >> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + data->regs = devm_ioremap_resource(dev, mem); > >We have devm_platform_ioremap_resource() for this now. > >> + if (IS_ERR(data->regs)) >> + return PTR_ERR(data->regs); >> + >> + data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk", >> + parent_data, >> + &plldig_clk_ops, >> + 0); >> + >> + ret = devm_clk_hw_register(dev, &data->hw); >> + if (ret) { >> + dev_err(dev, "failed to register %s clock\n", >> + dev->of_node->name); >> + return ret; >> + } >> + >> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, >> + &data->hw); >> + if (ret) { >> + dev_err(dev, "unable to add clk provider\n"); >> + return ret; >> + } >> + >> + /* >> + * The frequency of the VCO cannot be changed during runtime. >> + * Therefore, let the user specify a desired frequency. >> + */ >> + if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", >> + &data->vco_freq)) { >> + if (data->vco_freq < PLLDIG_MIN_VCO_FREQ || >> + data->vco_freq > PLLDIG_MAX_VCO_FREQ) >> + return -EINVAL; >> + } >> + >> + return plldig_init(&data->hw); >> +} >> + >> +static const struct of_device_id plldig_clk_id[] = { >> + { .compatible = "fsl,ls1028a-plldig"}, > >Nitpick: Add a space before } > >> + { } >> +}; >> +MODULE_DEVICE_TABLE(of, plldig_clk_id); >> + ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-13 0:06 ` Michael Walle @ 2019-12-16 17:55 ` Stephen Boyd 2019-12-17 7:08 ` [EXT] " Wen He 0 siblings, 1 reply; 10+ messages in thread From: Stephen Boyd @ 2019-12-16 17:55 UTC (permalink / raw) To: Li Yang, Mark Rutland, Michael Turquette, Michael Walle, Rob Herring, Wen He, devicetree, linux-clk, linux-kernel Quoting Michael Walle (2019-12-12 16:06:16) > Am 12. Dezember 2019 23:18:16 MEZ schrieb Stephen Boyd <sboyd@kernel.org>: > >Quoting Wen He (2019-12-04 23:26:53) > >> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, > >DPHY), > >> as implemented in TSMC CLN28HPM PLL, this PLL supports the > >programmable > >> integer division and range of the display output pixel clock's > >27-594MHz. > >> > >> Signed-off-by: Wen He <wen.he_1@nxp.com> > >> Signed-off-by: Michael Walle <michael@walle.cc> > > > >Is Michael the author? SoB chain is backwards here. > > the original driver was from Wen. I've just supplied some code and > the vco frequency stuff. so its basically a sob of us both. > > -michael Ok. That's a Co-developed-by: tag then. Thanks for letting us know. ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [EXT] Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-16 17:55 ` Stephen Boyd @ 2019-12-17 7:08 ` Wen He 2019-12-20 14:42 ` Michael Walle 0 siblings, 1 reply; 10+ messages in thread From: Wen He @ 2019-12-17 7:08 UTC (permalink / raw) To: Stephen Boyd, Leo Li, Mark Rutland, Michael Turquette, Michael Walle, Rob Herring, devicetree, linux-clk, linux-kernel > -----Original Message----- > From: Stephen Boyd <sboyd@kernel.org> > Sent: 2019年12月17日 1:56 > To: Leo Li <leoyang.li@nxp.com>; Mark Rutland <mark.rutland@arm.com>; > Michael Turquette <mturquette@baylibre.com>; Michael Walle > <michael@walle.cc>; Rob Herring <robh+dt@kernel.org>; Wen He > <wen.he_1@nxp.com>; devicetree@vger.kernel.org; linux-clk@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: [EXT] Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output > interface > > Caution: EXT Email > > Quoting Michael Walle (2019-12-12 16:06:16) > > Am 12. Dezember 2019 23:18:16 MEZ schrieb Stephen Boyd > <sboyd@kernel.org>: > > >Quoting Wen He (2019-12-04 23:26:53) > > >> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, > > >DPHY), > > >> as implemented in TSMC CLN28HPM PLL, this PLL supports the > > >programmable > > >> integer division and range of the display output pixel clock's > > >27-594MHz. > > >> > > >> Signed-off-by: Wen He <wen.he_1@nxp.com> > > >> Signed-off-by: Michael Walle <michael@walle.cc> > > > > > >Is Michael the author? SoB chain is backwards here. > > > > the original driver was from Wen. I've just supplied some code and the > > vco frequency stuff. so its basically a sob of us both. > > > > -michael > > Ok. That's a Co-developed-by: tag then. Thanks for letting us know. The v12 version patch was sent out. Does need I change the author sign to below? Co-developed-by: Wen He <wen.he_1@nxp.com> Signed-off-by: Wen He <wen.he_1@nxp.com> Co-developed-by: Michael Walle <michael.@walle.cc> Signed-off-by: Michael Walle <michael.@walle.cc> Signed-off-by: Wen He <wen.he_1@nxp.com> Best Regards, Wen ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [EXT] Re: [v11 2/2] clk: ls1028a: Add clock driver for Display output interface 2019-12-17 7:08 ` [EXT] " Wen He @ 2019-12-20 14:42 ` Michael Walle 0 siblings, 0 replies; 10+ messages in thread From: Michael Walle @ 2019-12-20 14:42 UTC (permalink / raw) To: Wen He Cc: Stephen Boyd, Leo Li, Mark Rutland, Michael Turquette, Rob Herring, devicetree, linux-clk, linux-kernel Am 2019-12-17 08:08, schrieb Wen He: >> -----Original Message----- >> From: Stephen Boyd <sboyd@kernel.org> >> Sent: 2019年12月17日 1:56 >> To: Leo Li <leoyang.li@nxp.com>; Mark Rutland <mark.rutland@arm.com>; >> Michael Turquette <mturquette@baylibre.com>; Michael Walle >> <michael@walle.cc>; Rob Herring <robh+dt@kernel.org>; Wen He >> <wen.he_1@nxp.com>; devicetree@vger.kernel.org; >> linux-clk@vger.kernel.org; >> linux-kernel@vger.kernel.org >> Subject: [EXT] Re: [v11 2/2] clk: ls1028a: Add clock driver for >> Display output >> interface >> >> Caution: EXT Email >> >> Quoting Michael Walle (2019-12-12 16:06:16) >> > Am 12. Dezember 2019 23:18:16 MEZ schrieb Stephen Boyd >> <sboyd@kernel.org>: >> > >Quoting Wen He (2019-12-04 23:26:53) >> > >> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, >> > >DPHY), >> > >> as implemented in TSMC CLN28HPM PLL, this PLL supports the >> > >programmable >> > >> integer division and range of the display output pixel clock's >> > >27-594MHz. >> > >> >> > >> Signed-off-by: Wen He <wen.he_1@nxp.com> >> > >> Signed-off-by: Michael Walle <michael@walle.cc> >> > > >> > >Is Michael the author? SoB chain is backwards here. >> > >> > the original driver was from Wen. I've just supplied some code and the >> > vco frequency stuff. so its basically a sob of us both. >> > >> > -michael >> >> Ok. That's a Co-developed-by: tag then. Thanks for letting us know. > > The v12 version patch was sent out. > Does need I change the author sign to below? I guess you mean the MODULE_AUTHOR()? I don't care if you add me or not, so do as you like. > Co-developed-by: Wen He <wen.he_1@nxp.com> > Signed-off-by: Wen He <wen.he_1@nxp.com> > Co-developed-by: Michael Walle <michael.@walle.cc> > Signed-off-by: Michael Walle <michael.@walle.cc> > Signed-off-by: Wen He <wen.he_1@nxp.com> Judging by the other Co-developed-by: lines it should be Co-developed-by: Michael Walle <michael.@walle.cc> Signed-off-by: Michael Walle <michael.@walle.cc> Signed-off-by: Wen He <wen.he_1@nxp.com> -michael ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings 2019-12-05 7:26 [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Wen He 2019-12-05 7:26 ` [v11 2/2] clk: ls1028a: Add clock driver for Display output interface Wen He @ 2019-12-05 14:26 ` Rob Herring 2019-12-06 3:01 ` [EXT] " Wen He 1 sibling, 1 reply; 10+ messages in thread From: Rob Herring @ 2019-12-05 14:26 UTC (permalink / raw) To: Wen He Cc: Michael Turquette, Stephen Boyd, Mark Rutland, Michael Walle, Li Yang, devicetree, linux-clk, linux-kernel On Thu, Dec 05, 2019 at 03:26:52PM +0800, Wen He wrote: > LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display > output interface. Add a YAML schema for this. > > Signed-off-by: Wen He <wen.he_1@nxp.com> > Signed-off-by: Michael Walle <michael@walle.cc> > --- > change in v11: > - renamed 'vco-frequency' to 'fsl,vco-hz' to clearly feild definiation > > .../devicetree/bindings/clock/fsl,plldig.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > new file mode 100644 > index 000000000000..23cce65b3a93 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding > + > +maintainers: > + - Wen He <wen.he_1@nxp.com> > + > +description: | > + NXP LS1028A has a clock domain PXLCLK0 used for the Display output > + interface in the display core, as implemented in TSMC CLN28HPM PLL. > + which generate and offers pixel clocks to Display. > + > +properties: > + compatible: > + const: fsl,ls1028a-plldig > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 0 > + > + fsl,vco-hz: > + $ref: '/schemas/types.yaml#/definitions/uint32' Drop this as '*-hz' already has a type. With that, Reviewed-by: Rob Herring <robh@kernel.org> > + description: Optional for VCO frequency of the PLL in Hertz. > + The VCO frequency of this PLL cannot be changed during runtime > + only at startup. Therefore, the output frequencies are very > + limited and might not even closely match the requested frequency. > + To work around this restriction the user may specify its own > + desired VCO frequency for the PLL. > + minimum: 650000000 > + maximum: 1300000000 > + default: 1188000000 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +examples: > + # Display PIXEL Clock node: > + - | > + dpclk: clock-display@f1f0000 { > + compatible = "fsl,ls1028a-plldig"; > + reg = <0x0 0xf1f0000 0x0 0xffff>; > + #clock-cells = <0>; > + clocks = <&osc_27m>; > + }; > + > +... > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [EXT] Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings 2019-12-05 14:26 ` [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Rob Herring @ 2019-12-06 3:01 ` Wen He 0 siblings, 0 replies; 10+ messages in thread From: Wen He @ 2019-12-06 3:01 UTC (permalink / raw) To: Rob Herring Cc: Michael Turquette, Stephen Boyd, Mark Rutland, Michael Walle, Leo Li, devicetree, linux-clk, linux-kernel > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2019年12月5日 22:27 > To: Wen He <wen.he_1@nxp.com> > Cc: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Michael Walle > <michael@walle.cc>; Leo Li <leoyang.li@nxp.com>; > devicetree@vger.kernel.org; linux-clk@vger.kernel.org; > linux-kernel@vger.kernel.org > Subject: [EXT] Re: [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A > Display Clock bindings > > Caution: EXT Email > > On Thu, Dec 05, 2019 at 03:26:52PM +0800, Wen He wrote: > > LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to > > Display output interface. Add a YAML schema for this. > > > > Signed-off-by: Wen He <wen.he_1@nxp.com> > > Signed-off-by: Michael Walle <michael@walle.cc> > > --- > > change in v11: > > - renamed 'vco-frequency' to 'fsl,vco-hz' to clearly feild > > definiation > > > > .../devicetree/bindings/clock/fsl,plldig.yaml | 55 > > +++++++++++++++++++ > > 1 file changed, 55 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > new file mode 100644 > > index 000000000000..23cce65b3a93 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fschemas%2Fbindings%2Fclock%2Ffsl%2Cplldig.yaml%23& > da > > > +ta=02%7C01%7Cwen.he_1%40nxp.com%7Cbc3e7eabcfef4f75316e08d7798f > 2c2e%7C > > > +686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63711152813315072 > 4&sda > > > +ta=vFRvWaWgdyIWqQAVE7NXnUKCnE%2BU38svA%2BjWqNc%2Fb8w%3D&a > mp;reserved= > > +0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=02%7C01%7Cwen > .he_1% > > > +40nxp.com%7Cbc3e7eabcfef4f75316e08d7798f2c2e%7C686ea1d3bc2b4c6f > a92cd9 > > > +9c5c301635%7C0%7C0%7C637111528133150724&sdata=dqj%2FBK%2 > F4%2BBmfk > > +HkGjeNZm3FZZlTYPJOzEKroyH0jKDA%3D&reserved=0 > > + > > +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding > > + > > +maintainers: > > + - Wen He <wen.he_1@nxp.com> > > + > > +description: | > > + NXP LS1028A has a clock domain PXLCLK0 used for the Display output > > + interface in the display core, as implemented in TSMC CLN28HPM PLL. > > + which generate and offers pixel clocks to Display. > > + > > +properties: > > + compatible: > > + const: fsl,ls1028a-plldig > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 0 > > + > > + fsl,vco-hz: > > + $ref: '/schemas/types.yaml#/definitions/uint32' > > Drop this as '*-hz' already has a type. > > With that, > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks a lot; Best Regards, Wen > > > + description: Optional for VCO frequency of the PLL in Hertz. > > + The VCO frequency of this PLL cannot be changed during runtime > > + only at startup. Therefore, the output frequencies are very > > + limited and might not even closely match the requested > frequency. > > + To work around this restriction the user may specify its own > > + desired VCO frequency for the PLL. > > + minimum: 650000000 > > + maximum: 1300000000 > > + default: 1188000000 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - '#clock-cells' > > + > > +examples: > > + # Display PIXEL Clock node: > > + - | > > + dpclk: clock-display@f1f0000 { > > + compatible = "fsl,ls1028a-plldig"; > > + reg = <0x0 0xf1f0000 0x0 0xffff>; > > + #clock-cells = <0>; > > + clocks = <&osc_27m>; > > + }; > > + > > +... > > -- > > 2.17.1 > > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-12-20 14:42 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-12-05 7:26 [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Wen He 2019-12-05 7:26 ` [v11 2/2] clk: ls1028a: Add clock driver for Display output interface Wen He 2019-12-09 9:13 ` Wen He 2019-12-12 22:18 ` Stephen Boyd 2019-12-13 0:06 ` Michael Walle 2019-12-16 17:55 ` Stephen Boyd 2019-12-17 7:08 ` [EXT] " Wen He 2019-12-20 14:42 ` Michael Walle 2019-12-05 14:26 ` [v11 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings Rob Herring 2019-12-06 3:01 ` [EXT] " Wen He
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