On Mon, Dec 23, 2019 at 12:14:34AM +0300, Dmitry Osipenko wrote:
> 21.12.2019 01:26, Sowjanya Komatineni пишет:
> > Tegra PMC clock clk_out_1 is dedicated for audio mclk from Tegra30
> > through Tegra210 and currently Tegra clock driver does initial parent
> > configuration for audio mclk "clk_out_1" and enables them by default.

Please delete unneeded context from mails when replying.  Doing this
makes it much easier to find your reply in the message, helping ensure
it won't be missed by people scrolling through the irrelevant quoted
material.

> > -	clk_disable_unprepare(data->clk_cdev1);
> > -	clk_disable_unprepare(data->clk_pll_a_out0);
> > -	clk_disable_unprepare(data->clk_pll_a);
> > +	if (__clk_is_enabled(data->clk_cdev1))
> > +		clk_disable_unprepare(data->clk_cdev1);

> The root of the problem is that you removed clocks enabling from
> tegra_asoc_utils_init().

> I'm not sure why clocks should be disabled during the rate-changing,
> probably this action is not really needed.

I know nothing about this particular device but this is not that
unusual a restriction for audio hardware, you often can't
robustly reconfigure the clocking for a device while it's active
due to issues in the hardware.  You often see issues with FIFOs
glitching or state machines getting stuck.  This may not be an
issue here but if it's something that's documented as a
requirement it's probably good to pay attention.