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From: Jian Hu <jian.hu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
	Neil Armstrong <narmstrong@baylibre.com>
Cc: Jian Hu <jian.hu@amlogic.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	Victor Wan <victor.wan@amlogic.com>,
	Chandle Zou <chandle.zou@amlogic.com>,
	<linux-clk@vger.kernel.org>, <linux-amlogic@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v5 2/5] clk: meson: add support for A1 PLL clock ops
Date: Fri, 27 Dec 2019 17:46:03 +0800
Message-ID: <20191227094606.143637-3-jian.hu@amlogic.com> (raw)
In-Reply-To: <20191227094606.143637-1-jian.hu@amlogic.com>

Compared with the previous SoCs, self-adaption module current
is newly added for A1, And there is no reset parm except the
fixed pll. In A1 PLL the PLL enable sequence is different, Using
the new power-on sequence to enable the PLL.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
 drivers/clk/meson/clk-pll.c | 40 ++++++++++++++++++++++++++++++++-----
 drivers/clk/meson/clk-pll.h |  2 ++
 2 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index ddb1e5634739..9eb7d465d123 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -283,10 +283,14 @@ static void meson_clk_pll_init(struct clk_hw *hw)
 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 
 	if (pll->init_count) {
-		meson_parm_write(clk->map, &pll->rst, 1);
+		if (MESON_PARM_APPLICABLE(&pll->rst))
+			meson_parm_write(clk->map, &pll->rst, 1);
+
 		regmap_multi_reg_write(clk->map, pll->init_regs,
 				       pll->init_count);
-		meson_parm_write(clk->map, &pll->rst, 0);
+
+		if (MESON_PARM_APPLICABLE(&pll->rst))
+			meson_parm_write(clk->map, &pll->rst, 0);
 	}
 }
 
@@ -294,9 +298,12 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
 {
 	struct clk_regmap *clk = to_clk_regmap(hw);
 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+	int ret = 0;
 
-	if (meson_parm_read(clk->map, &pll->rst) ||
-	    !meson_parm_read(clk->map, &pll->en) ||
+	if (MESON_PARM_APPLICABLE(&pll->rst))
+		ret = meson_parm_read(clk->map, &pll->rst);
+
+	if (ret || !meson_parm_read(clk->map, &pll->en) ||
 	    !meson_parm_read(clk->map, &pll->l))
 		return 0;
 
@@ -321,6 +328,23 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
 	/* do nothing if the PLL is already enabled */
 	if (clk_hw_is_enabled(hw))
 		return 0;
+	/*
+	 * Compared with the previous SoCs, self-adaption module current
+	 * is newly added for A1, keep the new power-on sequence to enable the
+	 * PLL.
+	 */
+	if (MESON_PARM_APPLICABLE(&pll->current_en)) {
+		/* Enable the pll */
+		meson_parm_write(clk->map, &pll->en, 1);
+		udelay(10);
+		/* Enable the pll self-adaption module current */
+		meson_parm_write(clk->map, &pll->current_en, 1);
+		udelay(40);
+		/* Enable lock detect module */
+		meson_parm_write(clk->map, &pll->l_detect, 1);
+		meson_parm_write(clk->map, &pll->l_detect, 0);
+		goto out;
+	}
 
 	/* Make sure the pll is in reset */
 	meson_parm_write(clk->map, &pll->rst, 1);
@@ -331,6 +355,7 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
 	/* Take the pll out reset */
 	meson_parm_write(clk->map, &pll->rst, 0);
 
+out:
 	if (meson_clk_pll_wait_lock(hw))
 		return -EIO;
 
@@ -343,10 +368,15 @@ static void meson_clk_pll_disable(struct clk_hw *hw)
 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 
 	/* Put the pll is in reset */
-	meson_parm_write(clk->map, &pll->rst, 1);
+	if (MESON_PARM_APPLICABLE(&pll->rst))
+		meson_parm_write(clk->map, &pll->rst, 1);
 
 	/* Disable the pll */
 	meson_parm_write(clk->map, &pll->en, 0);
+
+	/* Disable PLL internal self-adaption module current */
+	if (MESON_PARM_APPLICABLE(&pll->current_en))
+		meson_parm_write(clk->map, &pll->current_en, 0);
 }
 
 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 367efd0f6410..a2228c0fdce5 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -36,6 +36,8 @@ struct meson_clk_pll_data {
 	struct parm frac;
 	struct parm l;
 	struct parm rst;
+	struct parm current_en;
+	struct parm l_detect;
 	const struct reg_sequence *init_regs;
 	unsigned int init_count;
 	const struct pll_params_table *table;
-- 
2.24.0


  parent reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-27  9:46 [PATCH v5 0/5] add Amlogic A1 clock controller driver Jian Hu
2019-12-27  9:46 ` [PATCH v5 1/5] dt-bindings: clock: meson: add A1 PLL clock controller bindings Jian Hu
2020-01-03 22:29   ` Rob Herring
2020-01-10 15:36   ` Jerome Brunet
2020-01-16  5:50     ` Jian Hu
2019-12-27  9:46 ` Jian Hu [this message]
2019-12-27 16:53   ` [PATCH v5 2/5] clk: meson: add support for A1 PLL clock ops Martin Blumenstingl
2020-01-09  6:55     ` Jian Hu
2019-12-27  9:46 ` [PATCH v5 3/5] clk: meson: a1: add support for Amlogic A1 PLL clock driver Jian Hu
2019-12-27 17:04   ` Martin Blumenstingl
2020-01-09  7:55     ` Jian Hu
2019-12-27  9:46 ` [PATCH v5 4/5] dt-bindings: clock: meson: add A1 peripheral clock controller bindings Jian Hu
2020-01-10 15:38   ` Jerome Brunet
2020-01-16  6:19     ` Jian Hu
2019-12-27  9:46 ` [PATCH v5 5/5] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver Jian Hu
2019-12-27 17:22   ` Martin Blumenstingl
2020-01-09 11:11     ` Jian Hu

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