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[46.91.239.63]) by smtp.gmail.com with ESMTPSA id o4sm3932302wrw.97.2020.01.08.04.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2020 04:00:14 -0800 (PST) Date: Wed, 8 Jan 2020 13:00:13 +0100 From: Thierry Reding To: Stephen Warren Cc: Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH V3 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1 Message-ID: <20200108120013.GB1993114@ulmo> References: <20191003205033.98381-1-swarren@wwwdotorg.org> <20191003205033.98381-2-swarren@wwwdotorg.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0eh6TmSyL6TZE2Uz" Content-Disposition: inline In-Reply-To: <20191003205033.98381-2-swarren@wwwdotorg.org> User-Agent: Mutt/1.13.1 (2019-12-14) Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org --0eh6TmSyL6TZE2Uz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 03, 2019 at 02:50:31PM -0600, Stephen Warren wrote: > From: Stephen Warren >=20 > For a little over a year, U-Boot has configured the flow controller to > perform automatic RAM re-repair on off->on power transitions of the CPU > rail1]. This is mandatory for correct operation of Tegra124. However, RAM > re-repair relies on certain clocks, which the kernel must enable and > leave running. PLLP is one of those clocks. This clock is shut down > during LP1 in order to save power. Enable bypass (which I believe routes > osc_div_clk, essentially the crystal clock, to the PLL output) so that > this clock signal toggles even though the PLL is not active. This is > required so that LP1 power mode (system suspend) operates correctly. >=20 > The bypass configuration must then be undone when resuming from LP1, so > that all peripheral clocks run at the expected rate. Without this, many > peripherals won't work correctly; for example, the UART baud rate would > be incorrect. >=20 > NVIDIA's downstream kernel code only does this if not compiled for > Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's > downstream code makes this change conditional upon the active CPU > cluster. The upstream kernel currently doesn't support cluster switching, > so this patch doesn't test the active CPU cluster ID. >=20 > [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair >=20 > Reported-by: Jonathan Hunter > Cc: stable@vger.kernel.org > Signed-off-by: Stephen Warren > --- > v3: No change. > v2: No change. > --- > arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++ > 1 file changed, 11 insertions(+) Patches 2-4 applied to for-5.6/arm/core, thanks. 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